translating verilog primitive to vhdl

[EnezVeur]

Hello,
I am quite new to verilog. I need to translate a verilog primitive to vhdl
entity/architecture. This primitive is modelizing a latch with in, set,
clear, hold and notifier (?) inputs. Need some help. Some examples are
welcome

 

[M. Norton]

Hello,
I am quite new to verilog. I need to translate a verilog primitive to vhdl
entity/architecture. This primitive is modelizing a latch with in, set,
clear, hold and notifier (?) inputs. Need some help. Some examples are
welcome.

It would help to be able to see the declaration you're using for the
Verilog variant of the primitive structure. Given that, it shouldn't
be too difficult to create a VHDL version of that.

Best regards,
Mark Norton

 

[Jonathan Bromley]

Hello,
I am quite new to verilog. I need to translate a verilog primitive to vhdl
entity/architecture. This primitive is modelizing a latch with in, set,
clear, hold and notifier (?) inputs. Need some help. Some examples are
welcome

Sounds very homework-ish. A notifier is an output from a Verilog
timing check, used to signal that a timing violation has occurred.
Sometimes a latch or flip-flop may have a notifier *input* so that
when the notifier toggles, the storage element is loaded with X.

Since VHDL has nothing like Verilog's UDPs, the only hope is to
get a clear description of the Verilog primitive's functionality
and then to write a model of that functionality from scratch
in VHDL. Good luck.