trouble connecting an out std_logic_vector port to aggregate of signals

[ihk]

Hello,

Can a VHDL guru help me explaining why for a component defined like
this

component nios is
port (
pio_in : in std_logic_vector(15 downto 0),
pio_out : out std_logic_vector(7 downto 0)
);

I can do the following assignment:

nios_1 : nios
port map (
pio_in => (
0 => pll_locked,
1 => pll_clkswitch,
others => '0')
);

but the following gives syntax error (in Altera Quartus)

nios_1 : nios
port map (
pio_out => (
0 => led1,
1 => led2,
others => open)
);

The only way I can make this works is if I do the assignment to
pio_out like this:
nios_1 : nios
port map (
pio_out(0) => led1,
pio_out(1) => led2
);


Thanks and best regards,
Ivo

 

[Pontus]

Not beeing a guru, I should perhaps not attempt an answer...
(Gurus usually have several limo's, I don't)

I have been bitten by similar issues before, portmaps
where parts of a vector should connect, others stay open, etc.

I think this is an effect of the language trying to limit
the missuses rather than to allow non-precise statements
to be accepted. Or perhaps it's some vendors non-compliance
to the standard.

Your solution seems pretty clean and expressive, your
problem was probably getting the compiler to accept the code.

When I struggled with this, I got some informative compile
errors from the simulator (modelsim or riviera, can't remember witch).

HTH -- Pontus