two-dimensional array, assign to zero, vhdl

[--MMS--]

How can I initialize/assign all the bits of a two-dimensional array to
zero?

Below is part of my code:
-----------------------------------------------------------------------
SUBTYPE tags IS std_logic_vector (16 DOWNTO 0);


TYPE entry IS RECORD
-- valid : BOOLEAN;
tag : tags;
data: std_logic_vector(31 downto 0);
END RECORD;


TYPE eachCache IS ARRAY (sets) OF entry;

Type elCache is array (INTEGER RANGE 0 TO 1) of eachCache;

TYPE ww IS ARRAY(ways) OF ways;

Signal cache : elCache;
-------------------------------------------------------------------------

Specifically, what I wish to know is how to set all bits of signal
"cache" to zero.
It apparently works if I do....

cache(w)(s).data <= (others => '0');

....but I would like to know if I can do something like that in the
same line were I declare the signal. I have tried many alternatives,
but have not get the solution yet.



Thanks in advance,
MMS

 

[JK]

How can I initialize/assign all the bits of a two-dimensional array to
zero?

Below is part of my code:
-----------------------------------------------------------------------
SUBTYPE tags IS std_logic_vector (16 DOWNTO 0);

TYPE entry IS RECORD
-- valid : BOOLEAN;
tag : tags;
data: std_logic_vector(31 downto 0);
END RECORD;

TYPE eachCache IS ARRAY (sets) OF entry;

Type elCache is array (INTEGER RANGE 0 TO 1) of eachCache;

TYPE ww IS ARRAY(ways) OF ways;

Signal cache : elCache;
-------------------------------------------------------------------------

Specifically, what I wish to know is how to set all bits of signal
"cache" to zero.
It apparently works if I do....

cache(w)(s).data <= (others => '0');

...but I would like to know if I can do something like that in the
same line were I declare the signal. I have tried many alternatives,
but have not get the solution yet.

Thanks in advance,
MMS

type entry is record
tag : std_logic_vector(15 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eachCache is array(7 downto 0) of entry;
type elCache is array(1 downto 0) of eachCache;

signal cache : elCache;

process(reset, clock)
variable i, j : integer range 0 to 255;
begin
if reset='1' then
for i in elCache'range loop
for j in eachCache'range loop
cache(i)(j).tag <= (others => '0');
cache(i)(j).data <= (others => '0');
end loop;
end loop;
elsif rising_edge(clock) then
--bla bla bla
end if;
end process;

Regards,
JK

 

[Colin Paul Gloster]

--MMS-- <[email protected]> posted:

"How can I initialize[..]?

[..]"

N.B. a synthesis tool might not support initialization.

 

[Paul Uiterlinden]

How can I initialize/assign all the bits of a two-dimensional array to
zero?

Below is part of my code:
-----------------------------------------------------------------------
SUBTYPE tags IS std_logic_vector (16 DOWNTO 0);


TYPE entry IS RECORD
-- valid : BOOLEAN;
tag : tags;
data: std_logic_vector(31 downto 0);
END RECORD;


TYPE eachCache IS ARRAY (sets) OF entry;

Type elCache is array (INTEGER RANGE 0 TO 1) of eachCache;

TYPE ww IS ARRAY(ways) OF ways;

Signal cache : elCache;
-------------------------------------------------------------------------

Specifically, what I wish to know is how to set all bits of signal
"cache" to zero.
It apparently works if I do....

cache(w)(s).data <= (others => '0');

...but I would like to know if I can do something like that in the
same line were I declare the signal. I have tried many alternatives,
but have not get the solution yet.

Here is how it is done:

Signal cache : elCache :=
(
others =>
(
others =>
(
tag => (others => '0'),
data => (others => '0')
)
)
);

 

[Andy]

Here is how it is done:

Signal cache : elCache :=
(
others =>
(
others =>
(
tag => (others => '0'),
data => (others => '0')
)
)
);

Is there some reason why (others => (others => (others => (others =>
'0')))) does not work?

Andy

 

[Paul Uiterlinden]

Is there some reason why (others => (others => (others => (others =>
'0')))) does not work?

Because the lengths of tag and data differ. As far as I know, others can
only be used on arrays (array aggregates) and records (record aggregates).
The latter will only work if the type and length of the all record member
are the same. That is at least my understanding.

Indeed, modelsim reports an error on your code: 'Length of formal "data" is
32; length of actual is 17'. (tags was defined as slv(16 downto 0) and data
was defined as slv(31 downto 0)).

I can see the logic in that error message.

What would your code supposed to do if there was another record member with
type boolean, or even another record type?

 

[JK]

Because the lengths of tag and data differ. As far as I know, others can
only be used on arrays (array aggregates) and records (record aggregates).
The latter will only work if the type and length of the all record member
are the same. That is at least my understanding.

Oh. Thanx Paul.

Regards,
JK

 

[--MMS--]

THANKS!!!

 

[Andy]

What would your code supposed to do if there was another record member with
type boolean, or even another record type?

Well it would not work in that case. I assumed that if all record
elements were of the same type, they need not be the same length,
since each is statically determinable. Bad assumption apparently!

Thanks,

Andy