type error resolving infix expression -- ERROR

[senthil]

hi friends,

i have one type of signal that contains 64 values, each value of type
integer range -128 to 128. signal named as ifftre.

subtype addr is integer range 0 to 63.
type samp of array(addr) is integer range -128 to 128.
signal ifftre : samp;
subtype addr1 is integer range 0 to 79;
type samp1 of array(addr1) is integer range -128 to 128
signal cp : samp1;

i got on output over that signal. then i want to get an another output
of last 16 values with that of 64 values, total of 80 values i get and
store it in another signal.
for that i concatenate both values of same signal type

cp <= ifftre(48 to 63) & ifftre ;

and after i compile it

i found one Error, in vhdl Modelsim 5.5 SE
Error obtained as given below

Type Error resolving infix expression -- at the coding where cp
assigned.

pls give some suggestion over that..
expecting ur reply.

 

[Egbert Molenkamp]

hi friends,

i have one type of signal that contains 64 values, each value of type
integer range -128 to 128. signal named as ifftre.

subtype addr is integer range 0 to 63.
type samp of array(addr) is integer range -128 to 128.
signal ifftre : samp;
subtype addr1 is integer range 0 to 79;
type samp1 of array(addr1) is integer range -128 to 128
signal cp : samp1;

i got on output over that signal. then i want to get an another output
of last 16 values with that of 64 values, total of 80 values i get and
store it in another signal.
for that i concatenate both values of same signal type

cp <= ifftre(48 to 63) & ifftre ;

Remember that VHDL is a strongly type language. The type of cp is
not the same as that of ifftre.
Consider using an unconstrained array like:
type samp is array(natural range <>) of integer range -128 to 128;
signal ifftre : samp(0 to 63);
signal cp : samp(0 to 79);

cp <= ifftre(48 to 63) & ifftre ;

Egbert Molenkamp