type/subtype definition in entity

[zhangpei]

I want to define a type related to entity generics, like an array in
the following codes. But It seems I have no places to put those
subtype/type statements in the entity. I can not use package to define
those subtype/type since there are related to entity generics.

Any solution or idea?

Thanks a lot,

Z
04/16/07

===============
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity ir is
-- Here is not correct
-- subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
-- type MY_UNSIGNED_VECTOR is array(natural range<>) of
MY_UNSIGNED;
generic (
EL_SIZE : POSITIVE := 16;
EL_COUNT : POSITIVE := 8
);
-- Here is not correct either
-- subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
-- type MY_UNSIGNED_VECTOR is array(natural range<>) of
MY_UNSIGNED;
port (
val_b : out MY_UNSIGNED_VECTOR (0 to EL_COUNT-1);
clk_i : in std_logic
...
);
end ir;

 

[Alan Fitch]

I want to define a type related to entity generics, like an array in
the following codes. But It seems I have no places to put those
subtype/type statements in the entity. I can not use package to define
those subtype/type since there are related to entity generics.

Any solution or idea?

Thanks a lot,

Z
04/16/07

===============
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity ir is
-- Here is not correct
-- subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
-- type MY_UNSIGNED_VECTOR is array(natural range<>) of
MY_UNSIGNED;
generic (
EL_SIZE : POSITIVE := 16;
EL_COUNT : POSITIVE := 8
);
-- Here is not correct either
-- subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
-- type MY_UNSIGNED_VECTOR is array(natural range<>) of
MY_UNSIGNED;
port (
val_b : out MY_UNSIGNED_VECTOR (0 to EL_COUNT-1);
clk_i : in std_logic
...
);
end ir;

Hi Z,

you must put the declarations in a package, e.g.

library ieee;
use ieee.std_logic_arith.all; -- prefer numeric_std, it's a standard
package mytypes is
subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
type MY_UNSIGNED_VECTOR is array(natural range<>) of MY_UNSIGNED;

end package mytypes;


Of course you then don't have access to the generic. So you need to
fix the generic size using a constant or the subtype itself, e.g.

package mytypes is
constant EL_SIZE : positive := 10;
subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
type MY_UNSIGNED_VECTOR is array(natural range<>) of MY_UNSIGNED;

end package mytypes;

You must make the package visible in front of the entity of course, e.g.

library mylib;
use mylib.mytypes.all;
library ieee;
....

entity...

assuming you compiled the package into library 'mytypes'

Does that help?

In Accellera VHDL2006 you can have package generics, which would be a
neater solution - but your tools must have 2006 support.

regards
Alan

 

[Andy]

Right now, there isn't a good way to handle what you want, exactly. As
Alan said, Accellera's 2006 std has the ability to invoke packages
with generics, which would do what you want.

For now, I would do one of two things:

First, the package for this entity could use a constant from another
package (a higher level project package) to get the sizes. BTW,
whenever I create packages that have typedefs, etc for an entity, I
them at the top of the same file that has the entity/arch in it. That
way, if you've compiled the entity/arch, you've also compiled the
package necessary to use it. I also often define a record type to hold
all the generics for the entity in that package. That way handling all
the generics up through the hierarchy gets easier. Higher level
packages for higher level entities reference the lower level entities'
packages' generic record definitions, and so on, all the way to the
top. So adding a new parameter for a lower level entity means adding
it only to the entity/arch/package that needs it, and to the top level
where it gets set. It gets automatically plumbed through all the
levels in between.

The second method would be to pack the entire array into one long SLV
(can be an unconstrained port). Then you can pass generics into the
entity that allow you to recompose the array from the SLV (or
decompose the array to drive the port). Not the prettiest solution,
but it works.

Hope this helps,

Andy

 

[zhangpei]

Thanks a lot for your useful suggestion and informations, Alan and
Andy.

Accellera VHDL 2006 ( which will be VHDL 2007 with minor changes?)
looks perfect for my need.

http://www.synthworks.com/papers/vhdl_accellera_lewis_marlug_2006_bw.pdf

type std_logic_matrix is array (natural range <>) of
std_logic_vector ;
-- constraining in declaration
signal A : std_logic_matrix(7 downto 0)(5 downto 0) ;

entity e is
port (
A : std_logic_matrix(7 downto 0)(5 downto 0) ;
.. . .
) ;

That makes VHDL more like C for 2-dimensional arrays.

Anyway, I will use other method to implement my needs.

Z