Types

[Sandeep]

Does anyone know how to achieve slv(8) to mean std_logic_vector(7
downto 0) ? The idea is to make signal/port declarations concise. But
I am guessing concise-VHDL is an oxymoron anyways !

Sandeep

 

[Kai Harrekilde-Petersen]

Does anyone know how to achieve slv(8) to mean std_logic_vector(7
downto 0) ? The idea is to make signal/port declarations concise. But
I am guessing concise-VHDL is an oxymoron anyways !

Declaring slv to be a subtype of std_logic_vector will get you
halfways. But how are you going to discriminate between
std_logic_vector(7 downto 0) and std_logic_vector(8) using your
notation? Also, there are vectors which do are not 'downto', and
ranges that down have zero as the lower bound (and for good reasons
too).

I really really don't think you want to do what you write.

Regards,


Kai

 

[Jim Lewis]

Does anyone know how to achieve slv(8) to mean std_logic_vector(7
downto 0) ? The idea is to make signal/port declarations concise. But
I am guessing concise-VHDL is an oxymoron anyways !

Sandeep

That is because legal VHDL code and ambiguous are prohibited.

So at the current time, this cannot be done, however,
it is an interesting question.

Can I create an unconstrained type definition that only allows
arrays to be a single direction and requires one side of the
array to be a particular value, such as 0. In this case,
a constraint as you propose above could be made non-ambiguous
and hence legal.

The syntax probably could not be: slv(8)
Consider the following example:

signal A : slv(8) ;
signal B : slv(4) ;
signal C : slv(4) ;
signal D : sl ;

A <= B & C ; -- easy
C <= A(4) ; -- meaning 3 downto 0 -- Easy
B <= A(7 downto 4) ; -- is this still permitted?
-- If not how do I get these bits?

D <= A(5) ; -- meaning bit 5 -- or does it mean 4 downto 0?


So if it could be added to the language, I think it would
require a different (), perhaps [].


I am not sure it buys me enough to be excited about it,
however, I will inquire.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Sandeep]

Thanks Jim. I havent thought about the ambiguity. For now I'll just
alias slv to std_logic_vector in an unconstrained way. So something
like ...

alias slv is std_logic_vector;
signal a : slv(3 downto 0);

Sandeep

Does anyone know how to achieve slv(8) to mean std_logic_vector(7
downto 0) ? The idea is to make signal/port declarations concise. But
I am guessing concise-VHDL is an oxymoron anyways !

Sandeep

That is because legal VHDL code and ambiguous are prohibited.

So at the current time, this cannot be done, however,
it is an interesting question.

Can I create an unconstrained type definition that only allows
arrays to be a single direction and requires one side of the
array to be a particular value, such as 0. In this case,
a constraint as you propose above could be made non-ambiguous
and hence legal.

The syntax probably could not be: slv(8)
Consider the following example:

signal A : slv(8) ;
signal B : slv(4) ;
signal C : slv(4) ;
signal D : sl ;

A <= B & C ; -- easy
C <= A(4) ; -- meaning 3 downto 0 -- Easy
B <= A(7 downto 4) ; -- is this still permitted?
-- If not how do I get these bits?

D <= A(5) ; -- meaning bit 5 -- or does it mean 4 downto 0?


So if it could be added to the language, I think it would
require a different (), perhaps [].


I am not sure it buys me enough to be excited about it,
however, I will inquire.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~