E
Elinore
hi
During both of 'mapping' and 'generate PROM' step in ISE 6.3, the
warning below is encountered.
------------------------------------------
WARNINGesignRules:372 - Netcheck: Gated clock. Clock net
R2_C_MUX__n0392 is
sourced by a combinatorial pin. This is not good design practice.
Use the CE
pin to control the loading of data into the flip-flop.
------------------------------------------
In C_MUX instance is just a state machine, composed of 3 processes.
I doubt that state machine creates a gated clock. I do not know how to
avoid this warning. Does anyone has this experience?
Thankyou in advance.
------------------------------------------
.....
process(reset,clock)
begin
if reset='1' then
Current_State <= S0;
elsif clock'event and clock='1' then
Current_State <= Next_State;
end if;
end process;
.....
process(Current_State,address_A) -- State Change
begin
case SC is
when S0 =>
if Adderss_A="100" then
Next_State <= S2; else
Next_State <= S0;
end if;
when S1 =>
end process;
.....
process(clock) --- Output Execution
begin
if clock'event and clock='1' then
case State is
end process;
....
------------------------------------------
During both of 'mapping' and 'generate PROM' step in ISE 6.3, the
warning below is encountered.
------------------------------------------
WARNINGesignRules:372 - Netcheck: Gated clock. Clock net
R2_C_MUX__n0392 is
sourced by a combinatorial pin. This is not good design practice.
Use the CE
pin to control the loading of data into the flip-flop.
------------------------------------------
In C_MUX instance is just a state machine, composed of 3 processes.
I doubt that state machine creates a gated clock. I do not know how to
avoid this warning. Does anyone has this experience?
Thankyou in advance.
------------------------------------------
.....
process(reset,clock)
begin
if reset='1' then
Current_State <= S0;
elsif clock'event and clock='1' then
Current_State <= Next_State;
end if;
end process;
.....
process(Current_State,address_A) -- State Change
begin
case SC is
when S0 =>
if Adderss_A="100" then
Next_State <= S2; else
Next_State <= S0;
end if;
when S1 =>
end process;
.....
process(clock) --- Output Execution
begin
if clock'event and clock='1' then
case State is
end process;
....
------------------------------------------