unconstrained structures

[Olaf Petzold]

Hi,

is there a way to create unconstrained structures, in the sense of:

package la_pkg is

type trigger_cond_t is
record
bitpattern_value : std_logic_vector;
bitpattern_mask : std_logic_vector;
edgepattern_value : std_logic_vector;
edgepattern_mask : std_logic_vector;
end record;

end la_pkg;

....

entity trigger is
generic(
BIT_WIDTH : positive := 8
);
port(
clk : in std_logic;
trigger_cond : in trigger_cond_t; ??(BIT_WIDTH-1 downto 0)
match : out std_logic := '0'
);
end entity;

Thanks
Olaf

 

[Mike Treseler]

is there a way to create unconstrained structures . . .

http://groups.google.com/groups?q=vhdl+port+record+direction

-- Mike Treseler

 

[Olaf Petzold]

http://groups.google.com/groups?q=vhdl+port+record+direction

Thanks, for the record I use only one (in) direction of the port. The
problem ist the unconstrained width of std_logic_vector. I've got a
syntax error, seems it's not allowed. Is there a work around to do
what I want?

Thanks
Olaf

 

[Charles, SAG]

There is sort of a work-around, if you use access types (pointers)
e.g.
-- Predefine, to allow usage in block 2)
type ty_data_seq;
type ty_dt_section;
type ty_trans_seq;

-- Block 2)
type ty_data_seq_ptr is access ty_data_seq;
type ty_dt_section_ptr is access ty_dt_section;
type ty_slv_ptr is access std_logic_vector;
type ty_trans_seq_ptr is access ty_trans_seq;

-- Give meaning to predefined types
type ty_data_seq is array (natural range <>) of ty_slv_ptr;
type ty_trans_seq is array (natural range <>) of character;

type ty_dt_section is record
adr : ty_slv_ptr;
adr_step : integer;
burst : std_logic_vector(2 downto 0);
command : character;
repeat : integer;
size : std_logic_vector(2 downto 0);
data_seq : ty_data_seq_ptr;
trans_seq : ty_trans_seq_ptr;
next_dbs : ty_dt_section_ptr;
end record;

The type ty_dt_section can however not be used as a signal type. Use it
for variables instead:
e.g.
process . . . .
variable v_dt_current : ty_dt_section_ptr;
. . . . .
begin
. . . . .
v_dt_current := new ty_dt_section;
. . . . .
if (v_flag_good) then
v_slv_ptr := new std_logic_vector(v_op_addr_slv'length -
1 downto 0);
v_slv_ptr.all := v_op_addr_slv;
v_dt_current.adr := v_slv_ptr;
else

Hope this helps,
regards,
Charles

 

[Mike Treseler]

No. Can't pass a generic to a type.
Best you can do is package a constant

-- Mike Treseler
______________________
library ieee;
use ieee.std_logic_1164.all;
package la_pkg is
constant BIT_WIDTH : positive := 8;
subtype vec_t is std_logic_vector(BIT_WIDTH-1 downto 0);
type trigger_cond_t is
record
bitpattern_value : vec_t;
bitpattern_mask : vec_t;
edgepattern_value : vec_t;
edgepattern_mask : vec_t;
end record;
end package la_pkg;

library ieee;
use ieee.std_logic_1164.all;
use work.la_pkg.all;
entity trigger is
port(
clk : in std_logic;
trigger_cond : in trigger_cond_t;
match : out std_logic
);
end entity;