R
Ram
Location : San Jose
Duration : 6+months
Hi Freinds ,
Please do send matching resumes along with contact details to
(e-mail address removed)
his openings in for an ASIC design Verification Engineer.
Job Description:
Work as an effective member of a team to achieve first-pass success in
the development, implementation, and verification of traffic management
ASICs. The person in this position will develop block and system-level
test benches and verification environments using Vera,
Verilog/SystemVerilog,The person will work closely with design and
validation teams in support of verification/validation efforts.
This position is for a design verification engineer with seven or more
years of experience, working on a large networking ASIC. The engineer
will work with the verification leads and designers to complete both
chip level and block level test plans, and the verification environment
architectures. Based on these specifications and guidance from the
verification leads, the engineer will assist in the implementation of
stimulus generators, behavioral checkers, and test cases. The engineer
will work with the designers to debug failing test cases.
The engineer will assist in:
- running and maintaining regressions
- running code coverage
- creating an environment for and running gate level simulations
- writing PERL scripts to augment the verification environment
- writing assertions to measure functional coverage
Requirements are:
-Prior experience using Vera
- Must be conversant in Verilog
- Must be familiar with scripting languages such as Perl
-Prior "Network ASIC" verfication is a plus but not required
Desired skills:
- Fluency in an object oriented HVL, preferably Vera
- Ability to write and debug Verilog
- Makefiles
- PERL scripting
- Expertise in constrained random verification techniques
They would like to get someone who has extensively used Vera on a
networking ASIC project.
If necessary, they can speak with people that have extensive Specman (e
language) experience with network chips instead of Vera, and pay to
have them trained.
Ram
Account Manager
(e-mail address removed)
408 239 4091
Duration : 6+months
Hi Freinds ,
Please do send matching resumes along with contact details to
(e-mail address removed)
his openings in for an ASIC design Verification Engineer.
Job Description:
Work as an effective member of a team to achieve first-pass success in
the development, implementation, and verification of traffic management
ASICs. The person in this position will develop block and system-level
test benches and verification environments using Vera,
Verilog/SystemVerilog,The person will work closely with design and
validation teams in support of verification/validation efforts.
This position is for a design verification engineer with seven or more
years of experience, working on a large networking ASIC. The engineer
will work with the verification leads and designers to complete both
chip level and block level test plans, and the verification environment
architectures. Based on these specifications and guidance from the
verification leads, the engineer will assist in the implementation of
stimulus generators, behavioral checkers, and test cases. The engineer
will work with the designers to debug failing test cases.
The engineer will assist in:
- running and maintaining regressions
- running code coverage
- creating an environment for and running gate level simulations
- writing PERL scripts to augment the verification environment
- writing assertions to measure functional coverage
Requirements are:
-Prior experience using Vera
- Must be conversant in Verilog
- Must be familiar with scripting languages such as Perl
-Prior "Network ASIC" verfication is a plus but not required
Desired skills:
- Fluency in an object oriented HVL, preferably Vera
- Ability to write and debug Verilog
- Makefiles
- PERL scripting
- Expertise in constrained random verification techniques
They would like to get someone who has extensively used Vera on a
networking ASIC project.
If necessary, they can speak with people that have extensive Specman (e
language) experience with network chips instead of Vera, and pay to
have them trained.
Ram
Account Manager
(e-mail address removed)
408 239 4091