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Hi everyone !!
I'm new to VHDL (read : 1 week experience).
I was wondering if it was possible to use port map inside a process. I want it to be processed as a sequential statement and not a concurrent statement. Similar to how functions are used in C. Is this possible in VHDL ? If not, is there any other way around ?
Thanks in Advance
I'm new to VHDL (read : 1 week experience).
I was wondering if it was possible to use port map inside a process. I want it to be processed as a sequential statement and not a concurrent statement. Similar to how functions are used in C. Is this possible in VHDL ? If not, is there any other way around ?
Thanks in Advance