Variable array size in entity

[FabM]

Hello,

I want to do a variable array size port configurable with generic
value. The goal is to have a generic variables port output.

I try this but it doesn't work, Xilinx ISE require type declaration at
the end of entity.

Entity rams_line is
generic
(
p_size : natural := 10; -- size (in bits) of pixel values
matrix_size : natural := 3; -- size of convolution matrix
);
type ltab is array(1 to matrix_size) of std_logic_vector(p_size-1
downto 0);
port
(
-- output/read
line_tab : out ltab
);
end entity;

If you have an idea ?

FabM

 

[Enes Erdin]

Have a look at

http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/80822837e3c69d8d/

Have a nice synthesis,

--enes

 

[Tricky]

Hello,

I want to do a variable array size port configurable with generic
value. The goal is to have a generic variables port output.

I try this but it doesn't work, Xilinx ISE require type declaration at
the end of entity.

Entity rams_line is
generic
(
    p_size : natural := 10;       -- size (in bits) of pixel values
    matrix_size : natural := 3;   -- size of convolution matrix
);
type ltab is array(1 to matrix_size) of std_logic_vector(p_size-1
downto 0);
port
(
    -- output/read
    line_tab : out ltab
);
end entity;

If you have an idea ?

FabM

VHDL 2008 supports type declarations in generics, but Im not sure
whether this is meant as full types or subtypes. But this is unlikely
to be supported by synthesis vendors for some time.

Otherwise, the only way to do this is by declaring the constants and
2d array type in a packing, and including the package in the design
file. The only problem is, until VHDL 2008, 2d arrays (of the style
you have) have to have the object dimension fixed. ie:

type ltab is array(natural range <>) of std_logic_vector(p_size-1
downto 0);

But, usually, things like word widths are set for an entire design, so
that shouldnt be a problem.

once you've fixed p_size in a package constant, you set set
matrix_size on an entity by entity basis, via the generic. You
actually dont even need this generic, you can just have this:

package setup_package is
constant P_SIZE : natural := 10;
type ltab is array(natural range <>) of std_logic_vector(P_SIZE-1
downto 0); --although I would probably recommend unsigneds instead of
std_logic-vector as you are doing arithmatic on these values.
end package setup_package;

etity rams_line is
port (
line_tab : out ltab
)
--inside entity code you can use attributes like 'range, 'high, 'low
to do the indexing

......

--inside architecture:
signal ent1_line_tab : ltab(1 to 3); -- MATRIX_SIZE = 3;

...

my_rams_line : entity work.rams_line
port map (
line_tab => ent1_line_tab --size implied from connecting signal
);

 

[FabM]

VHDL 2008 supports type declarations in generics, but Im not sure
whether this is meant as full types or subtypes. But this is unlikely
to be supported by synthesis vendors for some time.

Otherwise, the only way to do this is by declaring the constants and
2d array type in a packing, and including the package in the design
file. The only problem is, until VHDL 2008, 2d arrays (of the style
you have) have to have the object dimension fixed. ie:

type ltab is array(natural range <>) of std_logic_vector(p_size-1
downto 0);

But, usually, things like word widths are set for an entire design, so
that shouldnt be a problem.

once you've fixed p_size in a package constant, you set set
matrix_size on an entity by entity basis, via the generic. You
actually dont even need this generic, you can just have this:

package setup_package is
  constant P_SIZE      : natural := 10;
  type ltab is array(natural range <>) of std_logic_vector(P_SIZE-1
downto 0); --although I would probably recommend unsigneds instead of
std_logic-vector as you are doing arithmatic on these values.
end package setup_package;

etity rams_line is
port (
  line_tab : out ltab
)
--inside entity code you can use attributes like 'range, 'high, 'low
to do the indexing

.....

--inside architecture:
signal ent1_line_tab : ltab(1 to 3); -- MATRIX_SIZE = 3;

..

my_rams_line : entity work.rams_line
port map (
  line_tab => ent1_line_tab   --size implied from connecting signal
);

Thank you very much for your quick and detailed response. I will try
this.

FabM