vcd help

[vex_helix]

I have a 4kb memory unit in my design

When I use dumpvars; and dumpall; I get switching info on all my variables, wires except the memory. The memory unit is a simple 2D 1024 X 16 bit register. Has anyone experienced this problem?

I tried to manually reference a memory row by:
$dumpvars(0, testbench.main.virtual_mem0.mem[1023]);

But got an error in ModelSim saying argument 2 is invalid. If I just go $dumpvars(0, testbench.main.virtual_mem0.mem); No error but I still don't see any information from mem which is 2D register.

Thanks

 

[gzidude]

yup

isn't dumpvars a verilog thing? I'll look it up eventually.

 

[vex_helix]

Yes it is. Sorry to put this on a vhdl form but I am sure the same problem would happen with vhdl.

Basically in ModelSim I am unable to get vcd data from memories. Everything else is fine.