VHDL -> block diagram

[dave.bryan]

Hi,

Does anyone know of a tool which will import a set of VHDL design files
and produce a block diagram showing the component interconnections
(without any RTL
translation unlike Xilinx ISE schematic viewer) ?

Thanks

 

[Eric]

http://groups.google.com/group/comp...iagram+software&rnum=7&hl=en#4bcda5c163da6d03

 

[anupam]

hi,
Every simulation window has an option to see the schematic of the
design like
ncsim of cadence has simvision
debussy of novas shows schematic with good clarity ....

regards,
Anupam Jain

 

[Thomas Reinemann]

Hi,

Does anyone know of a tool which will import a set of VHDL design files
and produce a block diagram showing the component interconnections
(without any RTL
translation unlike Xilinx ISE schematic viewer) ?

I belive HDL Designer by Mentor has a HDL2Graphics feature. I never
tried it.

Bye Tom

 

[Marc Horemans]

indeed, ncsim has simvision to draw blockdiagrams and it works very nice!
You can use simvision for debugging your (top level) code as well.

 

[Mariusz]

indeed, ncsim has simvision to draw blockdiagrams and it works very nice!
You can use simvision for debugging your (top level) code as well.

Aldec's Active-HDL hac Code2Graphics that converts Verilog or VHDL to
Diagrams without simulation:

http://www.aldec.com/products/active-hdl/multimediademo/movies/code2graphics/
http://www.aldec.com/products/active-hdl/multimediademo/movies/code2fsm/


Also it has so called Advanced Dataflow that shows the interconnects and
interactions between processes and signals in the design when simulation
is initialized:

http://www.aldec.com/products/active-hdl/multimediademo/movies/advanced_dataflow/

Mariusz

 

[dave.bryan]

Mariusz & all who replied,

Thanks for the suggestions for s/w to show interconnection between
instantiated components in a VHDL design. I was looking for a low cost
solution to automate documentation of designs but it seems that I'd
have to outlay quite a bit of cash to get this feature (I'd get many
others with it though). I think I'll stick with the manual approach for
now!

Thanks
Dave

 

[Mike Treseler]

I was looking for a low cost
solution to automate documentation of designs but it seems that I'd
have to outlay quite a bit of cash to get this feature

emacs vhdl-mode speedbar will give you most of
what you want for zero cash:
http://opensource.ethz.ch/emacs/vhdl-mode.gif

-- Mike Treseler

 

[dave.bryan]

Mike,
Thanks for the suggestion but I'm looking for something that can
document a design that a non-HDL engineer can easily follow i.e. block
diagram.
Thanks
Dave

 

[childs.brian]

Mike,
Thanks for the suggestion but I'm looking for something that can
document a design that a non-HDL engineer can easily follow i.e. block
diagram.
Thanks
Dave

Hi Dave, try www.expressivesystems.com where there is a fully
functional demo download of Expressive-IV

Brian

 

[dave.bryan]

Brian,

I've looked at your software & it looks very interesting (the price is
nice too!). However it appears that it is unable to import an existing
VHDL design & convert it to a graphical representation which is what
I'm looking to do. Am I missing something ?

Dave

 

[Brian]

Brian,

I've looked at your software & it looks very interesting (the price is
nice too!). However it appears that it is unable to import an existing
VHDL design & convert it to a graphical representation which is what
I'm looking to do. Am I missing something ?

Dave

No, you are not missing anything Dave, it cannot import existing
designs. It is best used for new designs.

Perhaps for your next design...........


--

Cheers
Brian
___________________________________
Expressive Systems.
www.expressivesystems.com

 

[dave.bryan]

Brian

How 'easy' is it to add this functionality to the software? Is it on
the cards?

Dave

 

[Brian]

Brian

How 'easy' is it to add this functionality to the software? Is it on
the cards?

Dave

Dave, it has been on the cards in the past but it is not easy to do it
sensibly, so you get a good layout which does not require to do a lot of
clean-up.

Our customers have always wanted us to do more enhancements to the
functionality instead. Once a company or user starts using the tool the
need to take in existing designs diminished rapidly so on-going
functionality is always more important so it's never got high on the
priority list. We can take in existing functionality as part of the
hierarchy of new designs making moving forward with the tool a little
less difficult.

--

Cheers
Brian
___________________________________
Expressive Systems.
www.expressivesystems.com

 

[info_]

Brian,

I've looked at your software & it looks very interesting (the price is
nice too!). However it appears that it is unable to import an existing
VHDL design & convert it to a graphical representation which is what
I'm looking to do. Am I missing something ?

Ease-VHDL does a nice job.
If you don't want to edit the result, most synthesis tools
now do that.

Bert

 

[dave.bryan]

Bert,

Thanks for the info. It looks like Easy VHDL does what I'm looking for
(not sure of the price yet though).

Dave

 

[Brian]

Bert,

Thanks for the info. It looks like Easy VHDL does what I'm looking for
(not sure of the price yet though).

Dave

Best of luck, hope it works for you (at a good price)

--

Cheers
Brian
___________________________________
Expressive Systems.
www.expressivesystems.com

 

[mr_haiko]

please help me!!!

Hi dear All
I would like to know what advantages VHDL from LabView FPGA.
What can I do by means of VHDL which I didn't do by means of LabView FPGA.

Best regards
Haik

P.S. Sorry for my English.

 

[JohnDuq]

Dave, what is wrong with the free version of the Xilinx software? If your design is too large for that it seems you could break it into smaller sections for documentation purposes.

Or is a schematic diagram not good enough, and you really need a block diagram? At that level of abstraction I don't believe you can leave it to a computer (I'm Sorry Dave...). Except maybe a really expensive package as you mentioned.

John