VHDL configuration

[skyworld]

Hi,

I'm a verilog user but now with some source code for VHDL in the
project. The configuration in VHDL source code confused me. Can
anybody help me to understand these questions? thanks very much!

1) I use modelsim as simulator. How does modelsim knows which
configuration is used?

2) there are several configurations for one module. If the top
configuration doesn't indicate which configuration is used, how do I
know which configuration is used for the module? e.g. suppose there
is
architecture rtl of module_a, architecture str of module_a,
architecture shell of module_a for entity module_a, and the top level
design is entity top_module. module_a is instanted in top_module, but
configuration in top_module doesn't indicate which architecture for
module_a is used. How do I know which architecture is instanted, rtl,
str or shell?

thanks.

skyworld

 

[Mike Treseler]

I'm a verilog user but now with some source code for VHDL in the
project. The configuration in VHDL source code confused me. Can
anybody help me to understand these questions? thanks very much!

Configurations are confusing, and like a fractal
pattern, things don't smooth out much as I zoom in.

Luckily there are other ways to handle options in vhdl.
For synthesis I use packages and for simulation
I use scripts, and default binding, as Alan demonstrated:

vsim tb(bench2)


-- Mike Treseler

 

[skyworld]

Your configurations should show up with a big letter 'C' next to them in
the library browser in the gui. You load that configuration by
highlighting it when starting simulation - or just double-click on it.

From a script,

# simulate configuration "myconfig"
vsim work.myconfig

If there are no letter 'C's in the library then you aren't using VHDL
configurations.

In that case if you have more than one testbench architecture, you can
pick the one to simulate by clicking on the '+' next to the testbench
entity (which will have 'E' for entity next to it) and highlighting and
simulating a particular testbench architecture.

From a script

# simulate architecture bench2 of entity tb
vsim tb(bench2)


This is known as "default binding" or "default configuration". The rule
is that the last compiled architecture is used, i.e. the architecture
with the latest timestamp.

regards
Alan

--
Alan Fitch
Senior Consultant

Doulos - Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: (e-mail address removed)
Fax: +44 (0)1425 471573 http://www.doulos.com

Hi Alan,

Thanks for your reply. please see my reply below:

Your configurations should show up with a big letter 'C' next to them in
the library browser in the gui. You load that configuration by
highlighting it when starting simulation - or just double-click on it.

[Ques]: I can't find this 'C' in the library bfowser in the gui, but
I'm sure the configuration is used because I checked the script, there
is a command:
vsim .... $DESIGN
and I'm sure $DESIGN is the configuration name. This parameter is one
of input parameters when I run the script with command line. Now I'm
totally confused by your explaination and results from gui/script.

This is known as "default binding" or "default configuration". The rule
is that the last compiled architecture is used, i.e. the architecture
with the latest timestamp.

[Ques]: How can I identify the "last compiled architecture/latest
timestamp"? I have to run the script with different configurations,
how do I know which architecture is used as last compiled? Is there
any clue for it? thanks very much.


regards
skyworld

 

[skyworld]

Configurations are confusing, and like a fractal
pattern, things don't smooth out much as I zoom in.

Luckily there are other ways to handle options in vhdl.
For synthesis I use packages and for simulation
I use scripts, and default binding, as Alan demonstrated:

vsim tb(bench2)

-- Mike Treseler

Hi Mike,

thanks for your reply. I have to use configuration because I'm in a
group and everyone must use it.


regards
skyworld

 

[Mike Treseler]

thanks for your reply. I have to use configuration because I'm in a
group and everyone must use it.

Then, presumable, someone in the group knows how to write one.
If so, they are easy to use, like Alan said:

vsim work.myconfig


-- Mike Treseler

 

[skyworld]

Then, presumable, someone in the group knows how to write one.
If so, they are easy to use, like Alan said:

vsim work.myconfig

-- Mike Treseler

well, the vhdl code are transfered from another group in the europe,
it is hard to ask when you find every small question.

 

[skyworld]

skyworld wrote:

Hi Alan,

Thanks for your reply. please see my reply below:

Your configurations should show up with a big letter 'C' next to them in
the library browser in the gui. You load that configuration by
highlighting it when starting simulation - or just double-click on it.

[Ques]: I can't find this 'C' in the library bfowser in the gui, but
I'm sure the configuration is used because I checked the script, there
is a command:
vsim .... $DESIGN

In that case, add

puts "$DESIGN"

in your Tcl script, i.e.

puts "$DESIGN"
vsim .... $DESIGN

and you'll see exactly what is being simulated.

and I'm sure $DESIGN is the configuration name. This parameter is one
of input parameters when I run the script with command line. Now I'm
totally confused by your explaination and results from gui/script.

This is known as "default binding" or "default configuration". The rule
is that the last compiled architecture is used, i.e. the architecture
with the latest timestamp.

[Ques]: How can I identify the "last compiled architecture/latest
timestamp"? I have to run the script with different configurations,
how do I know which architecture is used as last compiled? Is there
any clue for it? thanks very much.

You have to know what order the files were compiled in.
From the GUI, you can also see which architecture was picked in the
hierarchy browser for the simulation. E.g. you should see

module_a(RTL)

or something like that in the simulation browser.

You can also see when simulation loads, you should see messages like

Loading module_a(RTL)

in the output of Modelsim (i.e. the transcript window, or the transcript
log file)

regards
Alan

P.S. The best thing is to find someone else near you who can answer
these questions - not possible if you are working on your own though :-(

--
Alan Fitch
Senior Consultant

Doulos - Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: (e-mail address removed)
Fax: +44 (0)1425 471573 http://www.doulos.com

Hi Alan,

thanks for your reply. accroding to default binding, is there a way to
control this default binding, such as re-arrange the sequence of
configuration in the source code, or there are different configuration
in the different file for the same module, but I can arrange the
compile sequence of files to control default binding? does this make
sense? thanks.

 

[Mike Treseler]

well, the vhdl code are transfered from another group in the europe,
it is hard to ask when you find every small question.

http://groups.google.com/group/comp.lang.vhdl/search?group=comp.lang.vhdl&q=configuration