VHDL implementation of SPI for MAX6675

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Hi everyone,

I am new to this forum and I am new to VHDL...I am in deep trouble and would kindly request your help...

I have been asked to develop a VHDL code for SPI for the MAX6675...I have written some codes but the main problem I am facing is how to generate the chip select signal (CS).

I need to maintain the CS signal high for 220 ms to allow for the temperature conversion and then it must go low for 16 clock cycles to read the converted data bits...I do not know how to do that...

Please help me out...

Thank you,
Tarek
 
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Hi Tarek

You will have to scale down the clock in order to obtain a 220 ms CS signal.
Moreover do you need a SPI master: You could find inspiration in this code example.

Code:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Master is
    Port ( Master_Clk : in   STD_LOGIC;
			  Load :       in   STD_LOGIC;
			  Datain:      in   STD_LOGIC_VECTOR( 7 DOWNTO 0);
           SCLK : 		out  STD_LOGIC;
           MOSI : 		out  STD_LOGIC;
           MISO : 		in   STD_LOGIC;
			  SCS1:       out  STD_LOGIC);  -- Slave Chip Select#1 
end Master;

architecture Behavioral of Master is
   signal Shreg: STD_LOGIC_VECTOR( 7 DOWNTO 0) := "01100101";
   type   States is (Idle, Data_transfer, Stop);
	signal State: States := Idle;
	shared variable Count: integer range 0 to 8;
begin

   MOSI <= Shreg(7);
	SCLK <= Master_clk when State=Data_Transfer -- Master clock send to SCLK 
	   else '0';                       
	
process( Master_clk)
begin
     if rising_edge( Master_clk) then
            case State is
	   when Idle =>
	        SCS1 <= '1';
	        if Load='1' then
		Count := 0;  		-- Init Data bit counter
		Shreg <= Datain;  -- Load parallel data
		SCS1  <= '0';		-- Select Slave aktive
		State <= Data_Transfer; -- Change state
	        end if;
	  when Data_transfer =>
	        if Count<7 then 
		Count := Count+1;
		Shreg <= Shreg( 6 downto 0)& MISO; -- Shift
	       else
		State <= Stop;		 -- Change state
	       end if;
	  When Stop =>
 	       SCS1 <= '1';		 -- Deselect slave
	       if Load='0' then
		State <= Idle;		
	       end if;
	end case;
      end if;
end process;

end Behavioral;

More description of the code and topic can be found here: http://www.jjmk.dk/MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver2/index.htm

Your welcome
Jeppe
 
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How to implement PI Controller in VHDL

Thank you a lot for your generosity in sharing your codes...

I was wondering... Do you know how to implement a PI controller in VHDL... I have searched online but most of the codes are complex and I could not understand.

Please help me in that if you can.

Thank you,
Tarek
 
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Nice site jeppe! I love the way you show how there are so many different possibilities in VHDL to do solve a single problem in your examples section.
 
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Hi Jeppe,

Your site is really useful...thank you

I have gone through the SPI code it is really helpful but i could not understand the PI controller code it is a bit complex. I am actually using the PI controller to maintain the temperature of a heater.

Can you please provide me a description of the PI controller along with the testbench if possible.

Thank you,
Tarek
 
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Thanks for nice words - glad you found something usefull (both)
I agree - The PI section could be better and in fact do I need it for my class as well - lets say in less then two weeks.

Jeppe
 
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nice! Jeppe!

thanks for the code... but i could not understand.

''Integrator <= Integrator+Err/2;'' ----> std_logic_vector + integer??

''Actuator <= Yact;'' -----> waht ist the use of ''Actuator''?



Can you please provide me a testbench for the pi and pid controller??


thanks
 
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pmod tmp

i need a program for temperature measurement using pmod tmp, for nexys 2
somebody can help me?
tnk
 

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