Reply to thread

Message: [QUOTE="Wolfgang Grafen, post: 3158415"] Yes, I saw it and followed some examples before. Now I remember, I had problems describing and simulating a design composed of several modules. It is only me - I didn't know how to do it and I would like the documentation extended in this way. People who have to decide whether MyHDL will used for a project or not would like to see even more, a proof, e.g. a complete project, multiple clock domains, individual delays on signals (after...ns), asynchronous logic handling come in my mind. The developpers might know MyHDL can do all that, but naturally there is the fear that approaching the top from the bottom a system might fail somewhere inbetween. MyHDLs documentation is becoming better and better. I honour that. Just my 2 cents Wolfgang [/QUOTE]