VHDL Latches Inferred

[canis_majoris]

Hi all!
I a beginner with the vhdl code !
and I have some trouble compiling with fpga advantage !

here's the code :



ENTITY test_s IS

Port ( clk ,reset: std_logic;
A, B ,C , D , E, F, G, H, I, J: in std_logic_vector (15 downto 0) ;
S : out std_logic_vector (31 downto 0 )) ;
END ENTITY test_s;
--
ARCHITECTURE arch OF test_s IS
-- machine d'état
type state is (M0, M1, M2, M3);
--signal state_s:state;

--signaux intermediaires
signal Sout,S1, S2, S3, S4, S5, S6, S7, S8 : std_logic_vector (31 downto 0);
signal S8m :std_logic_vector (47 downto 0);

-- Declare current and next state signals
SIGNAL current_state : STATE;
SIGNAL next_state : STATE;

BEGIN

-----------------------------------------------------------------
clocked_proc : PROCESS ( clk,reset)
-----------------------------------------------------------------
BEGIN
IF (reset = '0') THEN
current_state <= M0;
ELSIF (clk'EVENT AND clk = '1') THEN
current_state <= next_state;
END IF;
END PROCESS clocked_proc;

-----------------------------------------------------------------
nextstate_proc : PROCESS (
current_state
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
WHEN M0 =>
next_state <= M1;
WHEN M1 =>
next_state <= M2;
WHEN M2 =>
next_state <= M3;
WHEN M3 =>
next_state <= M0;
WHEN OTHERS =>
next_state <= M0;
END CASE;
END PROCESS nextstate_proc;

-----------------------------------------------------------------
output_proc : PROCESS ( Sout,S1, S2, S3, S4, S5, S6, S7, S8, S8m ,A, B ,C , D , E, F, G, H, I, J ,current_state)
-----------------------------------------------------------------
BEGIN

-- Combined Actions
CASE current_state IS
WHEN M0 =>
S1 <= A * B;
S2 <= C * D;
S3 <= E * F;
S4 <= G * H;
WHEN M1 =>
S5 <= S1 + S2;
S6 <= S3 + I;
WHEN M2 =>
S7 <= S4 + S5;
S8m <= S6 * J;
S8 <= S8m (31 downto 0);
WHEN M3 =>
Sout <= S7 + S8;


WHEN OTHERS =>
NULL;
END CASE;
S <= Sout (31 downto 0);
END PROCESS output_proc;




END ARCHITECTURE arch;



I have one error and two warning

Line 75: ERROR, Latches Inferred: Latches are created for signals "S1, S2, S3, S4, S5, S6, S7, S8, S8m, Sout" for not being assigned values at all input conditions


Line 20: WARNING, Port "S" is not synchronized using a clocked sequential logic



Line 95: WARNING, Unsynchronized FSM outputs: FSM "test_s.arch" has an output "S" not registered inside a clocked sequential logic


PLEASE HELP!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

 

[eliascm]

State Machine

You can incorporate output_proc into nextstate_proc for example:

WHEN M0 =>
S1 <= A * B;
S2 <= C * D;
S3 <= E * F;
S4 <= G * H;
S5 <= (others => '0'); --or some other value
S6 <= (others => '0'); --or some other value
S7 <= (others => '0'); --or some other value
S8 <= (others => '0'); --or some other value

next_state <= M1;

This makes S1...S8 clocked. Note that if you don't account for S1...S8 in all of the states, latches will be inferred.

 

[Philippe.Faes]

Latches and registers

For the latches, make sure that each of the signals (S1, S2,...) gets assigned in each possible path of your combinational process. Either assign them in each "when" clause, or assign a default value to each signal before the "case" statement.

For synchronizing the output port S, you can put the assignment S <= Sout (31 downto 0); in your synchronous (clocked) process, right next to current_state <= next_state;

--
Philippe
sigasi.com