VHDL PLI

[Sanka Piyaratna]

Hi,

I was wondering if anyone know about VHDL PLI (Programming Language
Interface).

Cheers,

Sanka

 

[Ajeetha (www.noveldv.com)]

Hi,

I was wondering if anyone know about VHDL PLI (Programming Language
Interface).

Cheers,

Sanka

Look for VHPI standard, recently this was approved by Accellera
committee. VCS, NC and Aldec already supports it, not sure if Modelsim
does (they have their proprietary FLI). We at CVC (www.noveldv.com)
have inhouse expertise in this domain, if needed.

Regards
Ajeetha, CVC
www.noveldv.com

 

[HT-Lab]

Hi,

I was wondering if anyone know about VHDL PLI (Programming Language
Interface).

Cheers,

Sanka

Hi Sanka,

If you just want to add some C/C++ to your design (and not control the
simulation kernel from your C-code) then I would advice you to look at
SystemC which is probably much easier to use that the VHPI (or Modelsim's
FLI).

Hans
www.ht-lab.com

 

[Sanka Piyaratna]

Hi Hans,

Thanks for your reply.

Am I able to develop the testbench in systemC for the RTL in VHDL and
simulate them together?

Sanka

 

[Ajeetha (www.noveldv.com)]

Hi Sanka,

Hi Hans,

Thanks for your reply.

Am I able to develop the testbench in systemC for the RTL in VHDL and
simulate them together?

Yes you can. Usually tools give examples of how to do this. I have
done it with VCS-MX, let me know if you need help on that.


Regards
Ajeetha, CVC
www.noveldv.com

 

[Sanka Piyaratna]

Great, Thanks Ajeetha.

Sanka

Hi Sanka,



Yes you can. Usually tools give examples of how to do this. I have
done it with VCS-MX, let me know if you need help on that.


Regards
Ajeetha, CVC
www.noveldv.com

 

[omara007]

www.noveldv.com)]Hi[/url] Sanka,

On Mar 18, 3:19 pm, Sanka Piyaratna <[email protected]>
wrote:
> Hi Hans,
>
> Thanks for your reply.
>
> Am I able to develop the testbench in systemC for the RTL in VHDL and
> simulate them together?

Yes you can. Usually tools give examples of how to do this. I have
done it with VCS-MX, let me know if you need help on that.


Regards
Ajeetha, CVC
www.noveldv.com

But what is the gain of using SystemC TestBenches to test VHDL over normal VHDL-based testbenches ? .. can you give an example of useful functions that, for example, I can't find in typical VHDL environment .. or even hard to be implemented ?