VHDL - Second argument of writeline must have a constant value.

[srajendar]

Hello,
Please see this piece of code

The VHDL Code goes like this...................
.........................

entity dwt_1d_file is
generic(file_in : string := "data.txt";
file_out : string := "result.txt");
port (clk : in std_logic;
rst : in std_logic);
end dwt_1d_file;

architecture dwt_1d_file of dwt_1d_file is
file pix_file : text open read_mode is file_in;
file temp_file: text;
file res_file : text;
signal temp_1 : std_logic_vector(7 downto 0);
signal hpc_1 : std_logic_vector(7 downto 0);
signal lpc_1 : std_logic_vector(7 downto 0);
begin
dwt_1d_quant_1:dwt_1d_quant
port map(input=>temp_1,clk=>clk,rst=>rst,hpc=>hpc_1,lpc=>lpc_1);
process(clk,rst)
variable pix_line:line;
variable lpc_line:line;
variable hpc_line:line;
variable res_line:line;
variable open_ok:file_open_status;
variable read_ok:boolean;
variable i:integer range 0 to 14:=14;
variable pix_val:boundary_pix_array;
variable temp_2:bit_vector(7 downto 0);
begin
if (rst='1') then temp_1<=(others=>'0');
file_open(open_ok,res_file,file_out,write_mode);
file_close(res_file);
elsif (clk='1' and clk'event) then
if (not endfile(pix_file)) then
if (not(read_ok) and i=14) then
file_open(open_ok,temp_file,"temp.txt",write_mode);
writeline(temp_file,lpc_line);
writeline(temp_file,hpc_line);.
.
.
.
.
Here i get a problem with HDL Analyzer.
The problem is "Second argument of writeline must have a constant value"
How to overcome this?
Please send me some solution for this.
Thank You.