R
rossalbi
hi, i have writen a pice of code which should impliment a value on the
LEDs of my FPGA development board as the signal 'count' increases.
However it is going strait to the ' when others => LEDs <= "00000000";
' value.
any help would be much appreciated...
-- Declare signals
signal CLK : std_logic;
signal RST : std_logic;
signal Count : std_logic_vector(21 downto 0);
signal LEDs : std_logic_vector(7 downto 0);
signal LEDVal : std_logic_vector(7 downto 0);
signal Dir : std_logic;
begin
-- Tie unused signals
User_Signals <= "ZZZZZZZZ";
IO_CLK_N <= 'Z';
IO_CLK_P <= 'Z';
IO <= (0=>LEDs(0), 1=>LEDs(3), 41=>LEDs(4), 42=>LEDs(1),
43=>LEDs(4),
44=>LEDs(5), 45=>LEDs(2), 46=>LEDs(7), others => 'Z');
-- Clock divider
process (CLK, RST)
begin
if (RST='1') then
Count <= (others=>'0');
elsif (CLK'event and CLK='1') then
Count <= Count + 1;
end if;
end process;
process (CLK, RST)
begin
case Count is
when "0000000000000000000000" => LEDs <= "00000001";
when "0000000000000000000001" => LEDs <= "00000010";
when "0000000000000000000010" => LEDs <= "00000100";
when "0000000000000000000011" => LEDs <= "00001000";
when "0000000000000000000100" => LEDs <= "00001001";
.
.
when "0000000000000001111110" => LEDs <= "01000000";
when "0000000000000001111111" => LEDs <= "10000000";
when others => LEDs <= "00000000";
end case;
end process;
-- Instantiate interfaces component
LEDs of my FPGA development board as the signal 'count' increases.
However it is going strait to the ' when others => LEDs <= "00000000";
' value.
any help would be much appreciated...
-- Declare signals
signal CLK : std_logic;
signal RST : std_logic;
signal Count : std_logic_vector(21 downto 0);
signal LEDs : std_logic_vector(7 downto 0);
signal LEDVal : std_logic_vector(7 downto 0);
signal Dir : std_logic;
begin
-- Tie unused signals
User_Signals <= "ZZZZZZZZ";
IO_CLK_N <= 'Z';
IO_CLK_P <= 'Z';
IO <= (0=>LEDs(0), 1=>LEDs(3), 41=>LEDs(4), 42=>LEDs(1),
43=>LEDs(4),
44=>LEDs(5), 45=>LEDs(2), 46=>LEDs(7), others => 'Z');
-- Clock divider
process (CLK, RST)
begin
if (RST='1') then
Count <= (others=>'0');
elsif (CLK'event and CLK='1') then
Count <= Count + 1;
end if;
end process;
process (CLK, RST)
begin
case Count is
when "0000000000000000000000" => LEDs <= "00000001";
when "0000000000000000000001" => LEDs <= "00000010";
when "0000000000000000000010" => LEDs <= "00000100";
when "0000000000000000000011" => LEDs <= "00001000";
when "0000000000000000000100" => LEDs <= "00001001";
.
.
when "0000000000000001111110" => LEDs <= "01000000";
when "0000000000000001111111" => LEDs <= "10000000";
when others => LEDs <= "00000000";
end case;
end process;
-- Instantiate interfaces component