VHDL Software Tools

[ShortCircuit]

I am relatively new to VHDL and have been writing behavioral models for less then 6 months. Up until now I have purely used Altera Modelsim to write, compile & simulate my code.

I am now getting further into a design which I will have to synthesize, and have recently began using Xilinx ISE to make use of its resource estimates. So now I write code in the ISE, it appears to compile the code both on the ISE and the simulator, then it runs the simulation on the simulator.

To me this doesn't seem to be very well integrated, I am often switching back and fourth between the ISE to correct a bug etc. I've also noticed multiple instances of Modelsim open when I resimulated which isn't what I'm after.

Am I missing something here, or is this how everyone else works?
Also what tools does everyone else here use?

 

[QuestaTechnologies]

I'm not sure if you need any tool to simulate your design.
If so then you can use free VHDL, Verilog testbench generators
from www . questatechnologies . com . Send mails to
support @ questatechnologies . com for more information.