VHDL Type Mismatch error indexed name returns a value whose type does not match

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Please help me in solving the error since 2 weeks. This program a CPLD board, a switching board, LED board........ans we have to enlighten 8 LEDs when the corresponding push button is pressed from switch board.........This is the program purpose......

Error (10381): VHDL Type Mismatch error at CPLDBOARD_EB020_EPM7128.vhd(214): indexed name returns a value whose type does not match "IO8", the type of the target expression

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PACKAGE_GLOBAL_VARIABLE.vhd
1. --PACKAGE DECLARED TO MAKE USE OF GLOBAL VARIABLE(s)
2. -- AS SUPPORTED IN VHDL SINCE VHDL'93
3.
4. LIBRARY ieee;
5. USE ieee.std_logic_1164.all;
6. USE ieee.numeric_std.all;
7. USE ieee.std_logic_signed.all;
8.
9. PACKAGE global_variable IS
10.
11. TYPE IO8 IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
12. TYPE IO4 IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
13.
14. END PACKAGE;
CPLDBOARD_EB020_EPM7128.vhd
1. LIBRARY work;
2. USE work.global_variable.all;
3. LIBRARY ieee;
4. USE ieee.std_logic_1164.all;
5. USE ieee.numeric_std.all;
6. USE ieee.std_logic_signed.all;
7.
8. ENTITY SWITCHBOARD_EB007 IS
9. PORT (
10. CLK_IN_S: IN STD_LOGIC;
11. RESET_S: IN STD_LOGIC;
12. BIT_IN_SWITCH: IN IO8;
13. BIT_OUT_SWITCH: OUT IO8);
14. END SWITCHBOARD_EB007;
15.
16. ARCHITECTURE SWITCHES_PUSH_BUTTONS OF
17. SWITCHBOARD_EB007 IS
18.
19. BEGIN
20. PUSH_BUTTONS: PROCESS (CLK_IN_S, RESET_S)
21.
22. BEGIN
23. IF RESET_S = '1' THEN
24. FOR i IN 0 TO 7 LOOP
25. BIT_OUT_SWITCH(i) <= '0';
26. END LOOP;
27. ELSIF (CLK_IN_S'EVENT AND CLK_IN_S = '1') THEN
28. FOR j IN 0 TO 7 LOOP
29. IF BIT_IN_SWITCH(j) = '1' THEN
30. BIT_OUT_SWITCH(j) <= BIT_IN_SWITCH(j);
31. END IF;
32. END LOOP;
33. END IF;
34. END PROCESS PUSH_BUTTONS;
35. END SWITCHES_PUSH_BUTTONS;
36.
37. LIBRARY work;
38. USE work.global_variable.all;
39. LIBRARY ieee;
40. USE ieee.std_logic_1164.all;
41. USE ieee.numeric_std.all;
42. USE ieee.std_logic_signed.all;
43.
44. ENTITY LEDBOARD_EB004 IS
45. PORT (
46. CLK_IN_L: IN STD_LOGIC;
47. RESET_L: IN STD_LOGIC;
48. BIT_IN_LED: IN IO8;
49. D0, D1, D2, D3, D4, D5, D6, D7: OUT STD_LOGIC);
-- BLUE LEDS OR DEPENDS ON YOUR CHOICE (RED/ GREEN/ BLUE/ YELLOW LEDS)
50. END LEDBOARD_EB004;
51.
52. ARCHITECTURE ENLIGHTEN_LEDS OF
53. LEDBOARD_EB004 IS
54.
55. BEGIN
56. ENLIGHTEN_LEDS: PROCESS(CLK_IN_L, RESET_L)
57.
58. BEGIN
59. IF RESET_L = '1' THEN
60. D0 <= '0';
61. D1 <= '0';
62. D2 <= '0';
63. D3 <= '0';
64. D4 <= '0';
65. D5 <= '0';
66. D6 <= '0';
67. D7 <= '0';
68. ELSE
69. WAIT UNTIL CLK_IN_L = '1' AND CLK_IN_L'EVENT;
70. IF BIT_IN_LED(0) = '1' THEN
71. D0 <= BIT_IN_LED(0);
72. END IF;
73. IF BIT_IN_LED(1) = '1' THEN
74. D1 <= BIT_IN_LED(1);
75. END IF;
76. IF BIT_IN_LED(2) = '1' THEN
77. D2 <= BIT_IN_LED(2);
78. END IF;
79. IF BIT_IN_LED(3) = '1' THEN
80. D3 <= BIT_IN_LED(3);
81. END IF;
82. IF BIT_IN_LED(4) = '1' THEN
83. D4 <= BIT_IN_LED(4);
84. END IF;
85. IF BIT_IN_LED(5) = '1' THEN
86. D5 <= BIT_IN_LED(5);
87. END IF;
88. IF BIT_IN_LED(6) = '1' THEN
89. D6 <= BIT_IN_LED(6);
90. END IF;
91. IF BIT_IN_LED(7) = '1' THEN
92. D7 <= BIT_IN_LED(7);
93. END IF;
94. END IF;
95. END PROCESS ENLIGHTEN_LEDS;
96. END ENLIGHTEN_LEDS;
97.
98. LIBRARY work;
99. USE work.global_variable.all;
100. LIBRARY ieee;
101. USE ieee.std_logic_1164.all;
102. USE ieee.numeric_std.all;
103. USE ieee.std_logic_signed.all;
104.
105. ENTITY CPLD_Crystal_Clock_Generator IS PORT(
106. CLK_IN : IN STD_LOGIC;
107. CLK_OUT : OUT STD_LOGIC);
108. END CPLD_Crystal_Clock_Generator;
109.
110. ARCHITECTURE System_Clock OF
111. CPLD_Crystal_Clock_Generator IS
112.
113. BEGIN
114.
115. PROCESS (CLK_IN)
116.
117. BEGIN
118. CLK_OUT <= NOT CLK_IN;
119. END PROCESS;
120. END System_Clock;
121.
122. LIBRARY work;
123. USE work.global_variable.all;
124. LIBRARY ieee;
125. USE ieee.std_logic_1164.all;
126. USE ieee.numeric_std.all;
127. USE ieee.std_logic_signed.all;
128.
129. ENTITY CPLDBOARD_EB020_EPM7128 IS
130. PORT (
131. CLK_IN_CPLD: IN STD_LOGIC;
132. CLK_OUT_CPLD: OUT STD_LOGIC;
133. RESET_CPLD: IN STD_LOGIC;
134. PORT_CPLD_ARRAY1_DB9_PIN8TO1: INOUT STD_LOGIC;
135. PORT_CPLD_ARRAY2_DB9_PIN8TO1: INOUT STD_LOGIC;
136. PORT_CPLD_ARRAY3_DB9_PIN8TO1: INOUT STD_LOGIC;
137. PORT_CPLD_ARRAY4_DB9_PIN8TO1: INOUT STD_LOGIC;
138. PORT_CPLD_ARRAY5_DB9_PIN8TO1: INOUT STD_LOGIC;
139. PORT_CPLD_ARRAY6_DB9_PIN8TO1: INOUT STD_LOGIC;
140. PORT_CPLD_ARRAY7_DB9_PIN8TO1: INOUT STD_LOGIC;
141. SIGNAL PORT_CPLD1_DB9_PIN9: STD_LOGIC;
142. SIGNAL PORT_CPLD2_DB9_PIN9: STD_LOGIC;
143. SIGNAL PORT_CPLD3_DB9_PIN9: STD_LOGIC;
144. SIGNAL PORT_CPLD4_DB9_PIN9: STD_LOGIC;
145. SIGNAL PORT_CPLD5_DB9_PIN9: STD_LOGIC;
146. SIGNAL PORT_CPLD6_DB9_PIN9: STD_LOGIC;
147. SIGNAL PORT_CPLD7_DB9_PIN9: STD_LOGIC);
148. END CPLDBOARD_EB020_EPM7128;
149.
150. ARCHITECTURE PROGRAM_CPLDBOARD OF
151. CPLDBOARD_EB020_EPM7128 IS
152.
153. TYPE GND9 IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
154.
155. COMPONENT CPLD_Crystal_Clock_Generator
156. PORT (CLK_IN_CPLD: IN STD_LOGIC;
157. CLK_OUT_CPLD: OUT STD_LOGIC);
158. END COMPONENT;
159. COMPONENT LEDBOARD_EB004
160. PORT (CLK_IN_L, RESET_L: IN STD_LOGIC;
161. BIT_IN_LED: IN IO8;
162. BIT_OUT_LED: OUT IO8);
163. END COMPONENT;
164. COMPONENT SWITCHBOARD_EB007
165. PORT (CLK_IN_S, RESET_S: IN STD_LOGIC;
166. BIT_IN_SWITCH: IN IO8;
167. BIT_OUT_SWITCH: OUT IO8);
168. END COMPONENT;
169. COMPONENT PORT_CPLD1
170. PORT (PORT_CPLD_ARRAY1_DB9_PIN8TO1: IO8;
171. SIGNAL PORT_CPLD1_DB9_PIN9: GND9);
172. END COMPONENT;
173. COMPONENT PORT_CPLD2
174. PORT (PORT_CPLD_ARRAY2_DB9_PIN8TO1: IO8;
175. SIGNAL PORT_CPLD2_DB9_PIN9: GND9);
176. END COMPONENT;
177. COMPONENT PORT_CPLD3
178. PORT (PORT_CPLD_ARRAY3_DB9_PIN8TO1: IO8;
179. SIGNAL PORT_CPLD3_DB9_PIN9: GND9);
180. END COMPONENT;
181. COMPONENT PORT_CPLD4
182. PORT (PORT_CPLD_ARRAY4_DB9_PIN8TO1: IO8;
183. SIGNAL PORT_CPLD4_DB9_PIN9: GND9);
184. END COMPONENT;
185. COMPONENT PORT_CPLD5
186. PORT (PORT_CPLD_ARRAY5_DB9_PIN8TO1: IO8;
187. SIGNAL PORT_CPLD5_DB9_PIN9: GND9);
188. END COMPONENT;
189. COMPONENT PORT_CPLD6
190. PORT (PORT_CPLD_ARRAY6_DB9_PIN8TO1: IO8;
191. SIGNAL PORT_CPLD6_DB9_PIN9: GND9);
192. END COMPONENT;
193. COMPONENT PORT_CPLD7
194. PORT (PORT_CPLD_ARRAY7_DB9_PIN8TO1: IO8;
195. SIGNAL PORT_CPLD7_DB9_PIN9: GND9);
196. END COMPONENT;
197.
198. CONSTANT VCC: BIT := '1';
199. SIGNAL T: IO8;
200. SIGNAL Q: IO8;
201. SIGNAL CLK_INTERNAL: STD_LOGIC;
202.
203. BEGIN
204. stage0: CPLD_Crystal_Clock_Generator
205. PORT MAP (NOT CLK_IN_CPLD, CLK_INTERNAL);
206. stage1: PORT_CPLD1 PORT MAP (PORT_CPLD_ARRAY1_DB9_PIN8TO1(1) => T(0), PORT_CPLD1_DB9_PIN9(0) => '-');
207. stage2: PORT_CPLD1 PORT MAP (PORT_CPLD_ARRAY1_DB9_PIN8TO1(2) => T(1), PORT_CPLD1_DB9_PIN9(1) => '-');
208. stage3: PORT_CPLD1 PORT MAP (PORT_CPLD_ARRAY1_DB9_PIN8TO1(3) => T(2), PORT_CPLD1_DB9_PIN9(2) => '-');
209. stage4: PORT_CPLD1 PORT MAP (PORT_CPLD_ARRAY1_DB9_PIN8TO1(4) => T(3), PORT_CPLD1_DB9_PIN9(3) => '-');
210. stage5: PORT_CPLD1 PORT MAP (PORT_CPLD_ARRAY1_DB9_PIN8TO1(5) => T(4), PORT_CPLD1_DB9_PIN9(4) => '-');
211. stage6: PORT_CPLD1 PORT MAP (PORT_CPLD_ARRAY1_DB9_PIN8TO1(6) => T(5), PORT_CPLD1_DB9_PIN9(5) => '-');
212. stage7: PORT_CPLD1 PORT MAP (PORT_CPLD_ARRAY1_DB9_PIN8TO1(7) => T(6), PORT_CPLD1_DB9_PIN9(6) => '-');
213. stage8: PORT_CPLD1 PORT MAP (PORT_CPLD_ARRAY1_DB9_PIN8TO1(8) => T(7), PORT_CPLD1_DB9_PIN9(7) => '-');
214. stage9: SWITCHBOARD_EB007 PORT MAP (CLK_IN_CPLD, RESET_CPLD, T(0), Q(0));
215. stage10: SWITCHBOARD_EB007 PORT MAP (CLK_IN_CPLD, RESET_CPLD, T(1), Q(1));
216. stage11: SWITCHBOARD_EB007 PORT MAP (CLK_IN_CPLD, RESET_CPLD, T(2), Q(2));
217. stage12: SWITCHBOARD_EB007 PORT MAP (CLK_IN_CPLD, RESET_CPLD, T(3), Q(3));
218. stage13: SWITCHBOARD_EB007 PORT MAP (CLK_IN_CPLD, RESET_CPLD, T(4), Q(4));
219. stage14: SWITCHBOARD_EB007 PORT MAP (CLK_IN_CPLD, RESET_CPLD, T(5), Q(5));
220. stage15: SWITCHBOARD_EB007 PORT MAP (CLK_IN_CPLD, RESET_CPLD, T(6), Q(6));
221. stage16: SWITCHBOARD_EB007 PORT MAP (CLK_IN_CPLD, RESET_CPLD, T(7), Q(7));
222. stage17: LEDBOARD_EB004 PORT MAP (CLK_IN_CPLD, RESET_CPLD, Q(0), D0);
223. stage18: LEDBOARD_EB004 PORT MAP (CLK_IN_CPLD, RESET_CPLD, Q(1) , D1);
224. stage19: LEDBOARD_EB004 PORT MAP (CLK_IN_CPLD, RESET_CPLD, Q(2) , D2);
225. stage20: LEDBOARD_EB004 PORT MAP (CLK_IN_CPLD, RESET_CPLD, Q(3) , D3);
226. stage21: LEDBOARD_EB004 PORT MAP (CLK_IN_CPLD, RESET_CPLD, Q(4) , D4);
227. stage22: LEDBOARD_EB004 PORT MAP (CLK_IN_CPLD, RESET_CPLD, Q(5) , D5);
228. stage23: LEDBOARD_EB004 PORT MAP (CLK_IN_CPLD, RESET_CPLD, Q(6) , D6);
229. stage24: LEDBOARD_EB004 PORT MAP (CLK_IN_CPLD, RESET_CPLD, Q(7) , D7);
230. CLK_OUT_CPLD <= CLK_INTERNAL;
231. END PROGRAM_CPLDBOARD;
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