Vhdl Vga Controller Problem

A

andrea90

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity vga_ctrlr is
port
(
reset: in std_logic; -- reset
clock: in std_logic; -- clock
ired: in std_logic_vector(10 downto 0); --in red
igreen: in std_logic_vector(10 downto 0); -- in green
iblue: in std_logic_vector(10 downto 0); -- in blue

vga_synk: out std_logic;
vga_blank: out std_logic;
vga_clock: out std_logic;
vga_hs: out std_logic; -- horizontal sync
vga_vs: out std_logic; -- vertical sync
r: out std_logic; -- out red
g: out std_logic; --out green
b: out std_logic; --out blue
vga_x: out integer range 0 to 639;
vga_y: out integer range 0 to 479;
request: out std_logic);

end vga_ctrlr;

architecture behave of vga_ctrlr is
signal h_count: integer range 1 to 818; -- horizontal pixel counter
signal v_count: integer range 1 to 523; -- vertical line counter
signal vga_hs_p: std_logic;
signal vga_hs_d: std_logic;

constant h_total :integer :=818; --h_front+h_sync+h_back+h_act
constant h_sync :integer :=102;
constant h_back :integer :=51;
constant h_act :integer :=640;
constant h_front :integer :=25;
constant h_blank :integer :=128; --h_front+h_sync+h_back;

constant v_total :integer :=524; --v_front+v_sync+v_back+v_act
constant v_sync :integer :=2;
constant v_back :integer :=31;
constant v_act :integer :=480;
constant v_front :integer :=11;
constant v_blank :integer :=44; --v_front+v_sync+v_back;



--h_count

begin

process(clock,reset)
begin

if reset='0' then
h_count <= '0'; BROBLEM Here

elsif (clock'event and clock='1') then

if h_count=(h_total-1) then
h_count <= '1';
else
h_count <= h_count+1;
end if;
end if;
end process;

--vga_hs

process(clock,reset)
begin

if reset='0' then
vga_hs <= '1';

elsif (clock'event and clock='1') then

if h_count=(h_front-1) then
vga_hs <= '0';
elsif
h_count=h_front+(h_sync-1) then
vga_hs <= 1;
end if;
end if;
end process;

--vga_hs_d

process(clock,reset)
begin

if reset='0' then
vga_hs_p <= '1';

elsif (clock'event and clock='1') then

vga_hs_p <= vga_hs;
end if;
end process;
vga_hs_d <= (not vga_hs_p);

--v_count

process(clock,reset)
begin

if reset='0' then
v_count <= '0';

elsif (clock'event and clock='1') then

if (vga_hs_d='1') then
if (v_count=v_total-1) then
v_count <= '0';
else
v_count <= v_count+1;
end if;
end if;
end if;
end process;

--vga_vs

process(clock,reset)
begin
if reset='0' then
vga_vs<= '1';
elsif (clock'event and clock='1') then
if vga_hs_d='1' then
if v_count=v_front-1 then
vga_vs<=0;

elsif
v_count=v_front+(v_sync-1) then
vga_vs <= '1';

end if;
end if;
end if;
end process;
--vga_x

vga_x <= h_count-h_blank when
h_count>=h_blank
else
(others=>'0');
--vga_y

vga_y <= v_count-v_blank when
v_count>=v_blank
else
(others=>'0');

--request
request <='1';

--vga_blank

vga_blank <= request;

--vga_sync

vga_sync <='1';

--vga_clock

vga_clock <= not clock;

--r,g,b
r <= ired;
g <= igreen;
b <= iblue;

end behave;
THE PROBLIM IS Error (10316): VHDL error at vga_ctrlr.vhd(58): character ''0'' used but not declared for type "integer"
 
J

joris

Joined
Jan 29, 2009
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Uhm you should instead write
Code: 
h_count <= 0;
Note that '0' specifies a bit or so, while 0 specifies a number (integer/natural or so)
 
A

andrea90

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Jul 15, 2010
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity vga_ctrlr is
port
(
reset: in std_logic; -- reset
clock: in std_logic; -- clock
ired: in std_logic_vector(10 downto 0); --in red
igreen: in std_logic_vector(10 downto 0); -- in green
iblue: in std_logic_vector(10 downto 0); -- in blue

vga_sync: out std_logic;
vga_blank: out std_logic;
vga_clock: out std_logic;
vga_hs: out std_logic; -- horizontal sync
vga_vs: out std_logic; -- vertical sync
r: out std_logic_vector(10 downto 0); -- out red
g: out std_logic_vector(10 downto 0); --out green
b: out std_logic_vector(10 downto 0); --out blue
vga_x: out integer range 0 to 639;
vga_y: out integer range 0 to 479;
request: out std_logic);

end vga_ctrlr;

architecture behave of vga_ctrlr is
signal h_count: integer range 0 to 818; -- horizontal pixel counter
signal v_count: integer range 0 to 523; -- vertical line counter
signal vga_hs_p: std_logic;
signal vga_hs_d: std_logic;
signal vga_hs_a: std_logic;
signal irequest: std_logic;

constant h_total :integer :=818; --h_front+h_sync+h_back+h_act
constant h_sync :integer :=102;
constant h_back :integer :=51;
constant h_act :integer :=640;
constant h_front :integer :=25;
constant h_blank :integer :=128; --h_front+h_sync+h_back;

constant v_total :integer :=524; --v_front+v_sync+v_back+v_act
constant v_sync :integer :=2;
constant v_back :integer :=31;
constant v_act :integer :=480;
constant v_front :integer :=11;
constant v_blank :integer :=44; --v_front+v_sync+v_back;



--h_count

begin

process(clock,reset)
begin

if reset='0' then
h_count <= 0;

elsif (clock'event and clock='1') then

if h_count=(h_total-1) then
h_count <= 0;
else
h_count <= h_count+1;
end if;
end if;
end process;

--vga_hs

process(clock,reset)
begin

if reset='0' then
vga_hs <= '1';
vga_hs_a <= '1';
elsif (clock'event and clock='1') then

if h_count=(h_front-1) then
vga_hs <= '0';
vga_hs_a <= '1';
elsif
h_count=h_front+(h_sync-1) then
vga_hs <= '1';
vga_hs_a <= '1';
end if;
end if;
end process;


--vga_hs_d

process(clock,reset)
begin

if reset='0' then
vga_hs_p <= '1';

elsif (clock'event and clock='1') then

vga_hs_p <= vga_hs_a;
end if;
end process;
vga_hs_d <= (not vga_hs_p);

--v_count

process(clock,reset)
begin

if reset='0' then
v_count <= 0;

elsif (clock'event and clock='1') then

if (vga_hs_d='1') then
if (v_count=v_total-1) then
v_count <= 0;
else
v_count <= v_count+1;
end if;
end if;
end if;
end process;

--vga_vs

process(clock,reset)
begin
if reset='0' then
vga_vs<= '1';
elsif (clock'event and clock='1') then
if vga_hs_d='1' then
if v_count=v_front-1 then
vga_vs<='0';

elsif
v_count=v_front+(v_sync-1) then
vga_vs <= '1';

end if;
end if;
end if;
end process;
--vga_x

vga_x <= h_count-h_blank when
h_count>=h_blank
else
0;
--vga_y

vga_y <= v_count-v_blank when
v_count>=v_blank
else
0;

--request
irequest <= '1' when (h_blank =< h_count =< h_total-1) and (v_blank =< v_count =< v_total-1)
else '0';
request <= irequest;
--vga_blank

vga_blank <= irequest;

--vga_sync

vga_sync <='1';

--vga_clock

vga_clock <= not clock;

--r,g,b
r <= ired;
g <= igreen;
b <= iblue;
end behave;
Error (10500): VHDL syntax error at vga_ctrlr.vhd(162) near text "<"; expecting "(", or an identifier, or unary operator
 
J

joris

Joined
Jan 29, 2009
Messages
152
Reaction score
0
You mistyped "<=" (less or equal) as "=<"

However, this still doesn't work:
Code: 
(h_blank <= h_count <= h_total-1)
Say that the first comparison is evaluated; that gives,
Code: 
( *boolean* <= *integer* )
which will be rejected.

I'd define a help function "isBetween(lowest, val, highest)" like this:
Code: 
function isBetween(lowest, val, highest : integer) return boolean is
begin
  if (val < lowest) then
    return false;
  end if;
  return val <= highest;
end;

-- and use it like:
irequest <= '1' when isBetween(h_blank, h_count, h_total-1) and isBetween(v_blank, v_count, v_total-1) else '0';
 

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