S
Scott Connors
Hello all.
I am involved in a project where I need to provide a DVI display of a
camera input. Here are the technical specs of the matter:
I have a 125 Hz frame rate camera coming in to my FPGA. The camera
resolution is 640x480. It has the usual vsync and hsync signals, with
dead time in some spots. A typical camera.
On the other end, I have to feed a DVI display with a native
resolution of 1280x1024 and an optimal refresh rate of 60 Hz. A
typical DVI display.
At the moment I simply want to display the camera data in the upper
left corner (640x480) and just write black pixels for the rest of the
screen. So I am not worried about image resizing functions.
The main problem lies in crossing the clock domain for the system.
For use as video buffers I have 2-2MB SRAM's external to the FPGA. I
currently have an implementation where I read from one memory while
writing to the other memory. When I have read an entire frame of
data, I switch the memory operations. I begin reading at the
beginning of the new read memory and write to the what would be the
next memory location in the new write memory. Therefore, part of the
memory is one frame behind the current frame.
This does not cause a problem with the display until I move the
camera. At this point the image tears (a bad white line) throughout
the image until the motion stops. This can be very annoying and I
need to prevent this from happening.
I am wondering if anyone has completed a camera to display conversion
successfully using simple frame buffers or if anyone has any
suggestions on techniques to try.
Logic use is not a problem, as I am currently only using 5% of the
V-II Pro.
Thank you for your assistance.
~Scott
I am involved in a project where I need to provide a DVI display of a
camera input. Here are the technical specs of the matter:
I have a 125 Hz frame rate camera coming in to my FPGA. The camera
resolution is 640x480. It has the usual vsync and hsync signals, with
dead time in some spots. A typical camera.
On the other end, I have to feed a DVI display with a native
resolution of 1280x1024 and an optimal refresh rate of 60 Hz. A
typical DVI display.
At the moment I simply want to display the camera data in the upper
left corner (640x480) and just write black pixels for the rest of the
screen. So I am not worried about image resizing functions.
The main problem lies in crossing the clock domain for the system.
For use as video buffers I have 2-2MB SRAM's external to the FPGA. I
currently have an implementation where I read from one memory while
writing to the other memory. When I have read an entire frame of
data, I switch the memory operations. I begin reading at the
beginning of the new read memory and write to the what would be the
next memory location in the new write memory. Therefore, part of the
memory is one frame behind the current frame.
This does not cause a problem with the display until I move the
camera. At this point the image tears (a bad white line) throughout
the image until the motion stops. This can be very annoying and I
need to prevent this from happening.
I am wondering if anyone has completed a camera to display conversion
successfully using simple frame buffers or if anyone has any
suggestions on techniques to try.
Logic use is not a problem, as I am currently only using 5% of the
V-II Pro.
Thank you for your assistance.
~Scott