J
Joseph
Hi all,
I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim
only displays the input/output signals of the simulated top entity.
Is there a way of viewing the internal signals declared in the
architecture of the entity without adding them to the port outputs of
the simulated top entity?
Thanks very much
Regards
Joseph
I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim
only displays the input/output signals of the simulated top entity.
Is there a way of viewing the internal signals declared in the
architecture of the entity without adding them to the port outputs of
the simulated top entity?
Thanks very much
Regards
Joseph