[VirtexII + VHDL] problems with clock signals...

[Yttrium]

hey, i have to use a DCM as i need multiple clocks now the problem what that
they should be de-asserted (not active) before some signal, so i need some
CE signal. i tried to solve it like this:

ddr_clkx2 <= ddr_clkx2_out and locked;

were locked is the lock signal from the DCM and the ddr_clkx2_out is a clock
output from the DCM and it should be 0 as long as locked is 0.
but when i use this trick it gives me the following warning when making the
bitfile (with bitgen):

WARNINGesignRules:372 - Netcheck: Gated clock. Clock net _n0045 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.

so how should i implement it and what they mean with CE pin? well i know
what they mean but how should i implement it in VHDL?

thanx in advance,

kind regards,

Yttrium

hey, i have to use a DCM as i need multiple clocks now the problem what that
they should be de-asserted (not active) before some signal, so i need some
CE signal. i tried to solve it like this:

ddr_clkx2 <= ddr_clkx2_out and locked;

were locked is the lock signal from the DCM and the ddr_clkx2_out is a clock
output from the DCM and it should be 0 as long as locked is 0.
but when i use this trick it gives me the following warning when making the
bitfile (with bitgen):

WARNINGesignRules:372 - Netcheck: Gated clock. Clock net _n0045 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.

so how should i implement it and what they mean with CE pin? well i know
what they mean but how should i implement it in VHDL?

thanx in advance,

kind regards,

Yttrium

 

[David R Brooks]

The report is correct: you cannot pass clocks through logic & still
use the dedicated clock resources.
If you *must* do this (rather than, say, holding your flipflops reset
or disabled until LOCKED asserts), use a BUFGMUX to gate the clock.
This is the *only* safe way to switch a clock, in Xilinx devices.

Note that if you have a large number of loads for your "gated" clock,
you can use their CE inputs, so that essentially you have a CE tree
paralleling the clock tree. If you then attach the attribute BUFGCE to
the CE tree, the tools will infer just such a BUFGMUX as I described
above, and remove the CE tree.

See the Libraries Guide, item BUFGMUX, and the Constraints Guide,
item BUFGCE.

To infer the CE pin, something like:

process (CLK)
begin
if CLK'event and CLK = '1' then
if CE = '1' then -- Don't combine these IFs
OUTPUT <= INPUT;
end if;
end if;
end process;


:hey, i have to use a DCM as i need multiple clocks now the problem what that
:they should be de-asserted (not active) before some signal, so i need some
:CE signal. i tried to solve it like this:
:
:ddr_clkx2 <= ddr_clkx2_out and locked;
:
:were locked is the lock signal from the DCM and the ddr_clkx2_out is a clock
utput from the DCM and it should be 0 as long as locked is 0.
:but when i use this trick it gives me the following warning when making the
:bitfile (with bitgen):
:
:WARNINGesignRules:372 - Netcheck: Gated clock. Clock net _n0045 is sourced
:by a combinatorial pin. This is not good design practice. Use the CE pin to
:control the loading of data into the flip-flop.
:
:so how should i implement it and what they mean with CE pin? well i know
:what they mean but how should i implement it in VHDL?
:
:thanx in advance,
:
:kind regards,
:
:Yttrium
:
:hey, i have to use a DCM as i need multiple clocks now the problem what that
:they should be de-asserted (not active) before some signal, so i need some
:CE signal. i tried to solve it like this:
:
:ddr_clkx2 <= ddr_clkx2_out and locked;
:
:were locked is the lock signal from the DCM and the ddr_clkx2_out is a clock
utput from the DCM and it should be 0 as long as locked is 0.
:but when i use this trick it gives me the following warning when making the
:bitfile (with bitgen):
:
:WARNINGesignRules:372 - Netcheck: Gated clock. Clock net _n0045 is sourced
:by a combinatorial pin. This is not good design practice. Use the CE pin to
:control the loading of data into the flip-flop.
:
:so how should i implement it and what they mean with CE pin? well i know
:what they mean but how should i implement it in VHDL?
:
:thanx in advance,
:
:kind regards,
:
:Yttrium
: