Viterbi Decoder Implementation

[davefowler1987]

Good Afternoon Ladies and Gentlemen

First off all may I apologise if this is not in the correct location. But I am looking to design eventually in VHDL. (Can someone point me in right direction as where else to post!)

I am looking to implement a Viterbi Decoder - originally was going to buy a core from Xilinx but company are no longer allowing me to do so. (not enough money!!)

So I am looking at the Viterbi from the fundamentals.
I am using this link as an approximate guide to create the model.
"http :// mentronix. net/ documents /viterbi decoder.pdf"

I want to implement a K = 7 system. In the above example the image in regards to the Path Metric System uses a K = 4 system. How would I go about extending this to K = 7?

Thanks for your time

Kind regards

Dave