viterbi implementation on actel fpga

[pradeep]

hai,
i need to impliment viterbi decoder 1/2 rate,k=7,hard decision.i have
clearly understood the algorithm but in design can anybody help me?

 

[Mike Treseler]

i need to impliment viterbi decoder 1/2 rate,k=7,hard decision.i have
clearly understood the algorithm but in design can anybody help me?

Maybe google can
http://groups-beta.google.com/groups/search?q=viterbi+decoder+vhdl

Has this problem replaced the traffic light controller?

-- Mike Treseler

 

[pradeep]

Maybe google can
http://groups-beta.google.com/groups/search?q=viterbi+decoder+vhdl

Has this problem replaced the traffic light controller?

-- Mike Treseler

i am implememting viterbi decoder for frame synchronised data,so could
u able to give the vhdl code for specifications.thnks in advance

 

[Thomas Stanka]

Hi,

i am implememting viterbi decoder for frame synchronised data,so could
u able to give the vhdl code for specifications.thnks in advance

If you implement something, _you_ write the code, if Mike gives you
ready code fullfiling your spec, _he_ implemented the decoder. Maybe
you are looking for soft ips, which could be adopted to fit your
specification. Then why not starting with looking at opencores.org.
Anyway, I expect Mike (and a lot other here) to be able to provide you
the code after receiving the right amount of money. But it might be
cheaper to buy a ready developed soft ip.

bye Thomas

 

[pradeep]

Hi,


If you implement something, _you_ write the code, if Mike gives you
ready code fullfiling your spec, _he_ implemented the decoder. Maybe
you are looking for soft ips, which could be adopted to fit your
specification. Then why not starting with looking at opencores.org.
Anyway, I expect Mike (and a lot other here) to be able to provide you
the code after receiving the right amount of money. But it might be
cheaper to buy a ready developed soft ip.

thanks, actually i want the exact block diagrm from which i can meet
the timing requirement so.......