warning?

[Max]

the following code:

global_read: process (reset, reg_en, rd)
begin
if reset = '1' then
ctrl_data_bus <= (others => 'Z'); -- all warnings are here!
else
if rd = '1' then
case reg_en is
when "001" =>
ctrl_data_bus <= CONV_STD_LOGIC_VECTOR(prescaler_reg,8);
when "010" =>
ctrl_data_bus(0) <= ch_en;
when "100" =>
ctrl_data_bus(2 downto 0) <= probe_bus;
when others =>
ctrl_data_bus <= (others => 'Z');
end case;
end if;
end if;
end process;

give the following woranings:

WARNING:Xst:736 - Found 1-bit latch for signal
<Mtridata_ctrl_data_bus<7>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtridata_ctrl_data_bus<6>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtridata_ctrl_data_bus<5>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtridata_ctrl_data_bus<4>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtridata_ctrl_data_bus<3>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtridata_ctrl_data_bus<2>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtridata_ctrl_data_bus<1>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtridata_ctrl_data_bus<0>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtrien_ctrl_data_bus<7>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtrien_ctrl_data_bus<6>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtrien_ctrl_data_bus<5>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtrien_ctrl_data_bus<4>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtrien_ctrl_data_bus<3>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtrien_ctrl_data_bus<2>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtrien_ctrl_data_bus<1>> created at line 129.
WARNING:Xst:736 - Found 1-bit latch for signal
<Mtrien_ctrl_data_bus<0>> created at line 129.


WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<7>_0 is equivalent to
Mtrien_ctrl_data_bus<6>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<6>_0 is equivalent to
Mtrien_ctrl_data_bus<5>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<7>_0 is equivalent to
Mtrien_ctrl_data_bus<5>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<6>_0 is equivalent to
Mtrien_ctrl_data_bus<4>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<5>_0 is equivalent to
Mtrien_ctrl_data_bus<4>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<7>_0 is equivalent to
Mtrien_ctrl_data_bus<4>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<6>_0 is equivalent to
Mtrien_ctrl_data_bus<3>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<5>_0 is equivalent to
Mtrien_ctrl_data_bus<3>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<4>_0 is equivalent to
Mtrien_ctrl_data_bus<3>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<7>_0 is equivalent to
Mtrien_ctrl_data_bus<3>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<2>_0 is equivalent to
Mtrien_ctrl_data_bus<1>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<7>_0 is equivalent to
Mtrien_ctrl_data_bus<6>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<6>_0 is equivalent to
Mtrien_ctrl_data_bus<5>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<7>_0 is equivalent to
Mtrien_ctrl_data_bus<5>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<6>_0 is equivalent to
Mtrien_ctrl_data_bus<4>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<5>_0 is equivalent to
Mtrien_ctrl_data_bus<4>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<7>_0 is equivalent to
Mtrien_ctrl_data_bus<4>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<6>_0 is equivalent to
Mtrien_ctrl_data_bus<3>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<5>_0 is equivalent to
Mtrien_ctrl_data_bus<3>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<4>_0 is equivalent to
Mtrien_ctrl_data_bus<3>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<7>_0 is equivalent to
Mtrien_ctrl_data_bus<3>_0
WARNING:Xst:382 - Register Mtrien_ctrl_data_bus<2>_0 is equivalent to
Mtrien_ctrl_data_bus<1>_0


I don't know why, and I don't know how to correct them.

Any idea?

thanks

 

[Colin Marquardt]

the following code:

global_read: process (reset, reg_en, rd)
begin
if reset = '1' then
ctrl_data_bus <= (others => 'Z'); -- all warnings are here!
else

No default assignment for the output signals(s) here. This is the
safest way to assure that you won't get a latch.

if rd = '1' then
case reg_en is
when "001" =>
ctrl_data_bus <= CONV_STD_LOGIC_VECTOR(prescaler_reg,8);
when "010" =>
ctrl_data_bus(0) <= ch_en;

What should happen to the other elements of ctrl_data_bus
(ctrl_data_bus'high downto 1)?

when "100" =>
ctrl_data_bus(2 downto 0) <= probe_bus;

Same here.

when others =>
ctrl_data_bus <= (others => 'Z');
end case;

If you don't use a default assignment, you need an else path here for
the case that rd /= '1'.

end if;
end if;
end process;

give the following woranings:

WARNING:Xst:736 - Found 1-bit latch for signal
<Mtridata_ctrl_data_bus<7>> created at line 129.

*Always* assign *all* elements of a vector, as shown above.

HTH,
Colin

 

[eadgbe]

The equivalences warnings just mean that your prescaler_reg is
fixed at all 0's and the syn tool is tying them all together.

And as Colm has said, you coded up a latch. If that's what you intended,
fine, but synthesis tools like to warn you when you do it.

Bob