zlotawy said:
WARNING
hysDesignRules:372 - Gated clock. Clock net nx64089z1 is sourced
by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
What does it mean in practise?
What it means is that you have a net called "nx64089z1" which is the output
of some combinatorial logic (i.e. not a flip flop) and that "nx64089z1" is
then used somewhere to clock some flip flop..Something like
nx64089z1 <= a and b;
where 'a' and 'b' are some other signals. By the looks of the name, it
would appear that "nx64089z1" is some internal net that the synthesizer
created enroute to implementing your logic.
In an FPGA environment gated clocks are not good design practice because
they can not be implemented glitch free because of the way FPGAs implement
logic by using look up table memories. Those glitches then get propogated
to the clock input of whatever it is that you have being clocked by this
signal and having a glitchy clock is never a good idea.
1. Find out where net "nx64089z1" goes (i.e. what are the signals that have
"nx64089z1" as a clock).
2. Presumably you should recognize the signal name(s) of at least some of
the places where "nx64089z1" goes and relate that back to your VHDL/Verilog
design source files.
3. Now that you know where in the source code you have stuff that is
generating the gated clock logic you have to rewrite it to fix. How this
needs to get rewritten depends completely on your design so there are no
specific recommendations however usually one of the following two approaches
will work. In both cases I'm assuming that "nx64089z1" is as written above
(i.e. nx64089z1 <= a and b). Even if that's not the case, the two
approaches should give you enough clues to go on.
Fix 1: If 'a' is a free running clock and 'b' is some signal that you'd
like to use to disable the clock then replace all instances where a flip
flop is using a gated clock with something of the form....
process(a)
if rising_edge(a) then
if (b = '1') then
Put your clocked stuff here
end if;
end if;
end process;
Fix 2: If neither 'a' nor 'b' are free running, and you simply want to
clock some flip flop when 'a' and 'b' are both true then replace the thing
that is generating "nx64089z1" with the following process. Again, based on
the net name I'm guessing that you'll not find a signal called "nx64089z1"
explicitly in your design so this approach probably doesn't apply, but just
in case.
process(Clock) -- You'll need to have 'some' free running clock of some
sort
if rising_edge(Clock) then
nx64089z1 <= a and b;
end if;
end prcoess;
There are other scenarios but like I said which solution (or other
solutions) are appropriate depends on what exactly your design is trying to
accomplish.
KJ
