What are twisted ports

[parag_paul]

hi All,
I just came across a scenario where somebody was talking about twisted
ports .


How do we implement them with VHDL

thanks in advance

-Parag

 

[Paul Uiterlinden]

hi All,
I just came across a scenario where somebody was talking about twisted
ports .


How do we implement them with VHDL

Depends on what is meant by twisted ports. I guess it is "twisted pairs",
or balanced signals. The two signals should allways be inverted with
respect to each other: 0/1 or 1/0.

On the sending side you drive one output with the true (non-inverted) value
and the other with the inverted value.

On the receiving side I would use the non-inverted signal for data reception
and check if the other is always negated (e.g. by using an assertion).

 

[David R Brooks]

Depends on what is meant by twisted ports. I guess it is "twisted pairs",
or balanced signals. The two signals should allways be inverted with
respect to each other: 0/1 or 1/0.

On the sending side you drive one output with the true (non-inverted) value
and the other with the inverted value.

On the receiving side I would use the non-inverted signal for data reception
and check if the other is always negated (e.g. by using an assertion).

You may also want to check the documentation for the tools & FPGA you
are using: they often have specific library cells that should be used
for this purpose.
The senders are speed-matched on the two paths (taking into account the
delay in the inverter).
The receiver will be a true analog differential amplifier, to reject
common-mode noise.
These special devices give dramatically better performance than trying
to emulate them with generic logic.

 

[MikeShepherd564]

twisted ports

...I guess it is "twisted pairs"

That's a relief. I thought it was yet another technology to learn.

 

[David Spencer]

You may also want to check the documentation for the tools & FPGA you
are using: they often have specific library cells that should be used
for this purpose.
The senders are speed-matched on the two paths (taking into account the
delay in the inverter).
The receiver will be a true analog differential amplifier, to reject
common-mode noise.
These special devices give dramatically better performance than trying
to emulate them with generic logic.

There is another big difference between using a true differential output and
making your own with two complementary single-ended pins. In the case of the
latter, the resulting pair of connections is voltage differential, but not
current differential. In other words, the current flowing along each half of
the pair still returns through the ground connection. With a true
differential driver the current is differential too, meaning that it flows
out down one of the wires and back through the other. This allows routing
through cables without a ground.

 

[Paul Uiterlinden]

There is another big difference between using a true differential output
and making your own with two complementary single-ended pins. In the case
of the latter, the resulting pair of connections is voltage differential,
but not current differential. In other words, the current flowing along
each half of the pair still returns through the ground connection. With a
true differential driver the current is differential too, meaning that it
flows out down one of the wires and back through the other. This allows
routing through cables without a ground.

All good comments.

My reply was only with simulation/verification in mind.

 

[Dave Pollum]

That's a relief. I thought it was yet another technology to learn.

Ah.... twisted ports require a special tool to twist the ports just
right, so that the data is perfect. But if you're not careful, you
can twist the ports right off of the chip!

-Dave Pollum

 

[Peter]

hi All,
I just came across a scenario where somebody was talking about twisted
ports .

How do we implement them with VHDL

thanks in advance

-Parag

Maybe he meant how a vector is defined? "downto" vs "to"?
A function to reverse a vector has been presented in this group some
years ago.

/Peter