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Hi,
I use Matlab HDL Coder to generate VHDL code for my project. I am new to VHDL. One of the test signals is 'SnKDone'. I guess this signal name can tellsome the significant of the test purpose and it may be used by some VHDL programmer. Do you know what meaning it is?
Thanks,
I use Matlab HDL Coder to generate VHDL code for my project. I am new to VHDL. One of the test signals is 'SnKDone'. I guess this signal name can tellsome the significant of the test purpose and it may be used by some VHDL programmer. Do you know what meaning it is?
Thanks,