Davy a écrit :
Hi, rickman,
Thanks!
Can you tell me what's Nonpipelined bus mean?
Best regards,
Davy
A pipelined bus is a bus that join two point A and B but you add a
register (or more) on the way so it will take some clock cycle to
arrive(as much as register you add) So a nonpipelined is one without any
register
Pipelining a bus permit to break the critical path of the bus but it
adds latency. The delay will still be the same but the max frequency
will be increase.
ex :
port(
din : in std_logic(15 downto 0);
dout : out std_logic(15 downto 0)
);
....
signal bus : std_logic_vector(15 downto 0);
signal bus_reg : std_logic_vector(15 downto 0);
------------------------------------------------------------------------
--Nonpipelined bus
-- critical path= 12ns
-- latency =0 clock cycle
bus <= din;
dout <= bus;
------------------------------------------------------------------------
--Pipelined bus (1 register)
-- critical path = 6ns
-- latency =1 clock cycle
process(clk)
begin
if rising_edge(clk) then
bus <= din;
end;
dout <= bus;
------------------------------------------------------------------------
--Pipelined bus (2 registers)
-- critical path = 4ns
-- latency =2 clock cycle
process(clk)
begin
if rising_edge(clk) then
bus <= din;
dout <= bus;
end;
------------------------------------------------------------------------
--Pipelined bus (3 registers)
-- critical path = 3ns
-- latency =2 clock cycle
process(clk)
begin
if rising_edge(clk) then
bus <= din;
bus_reg <= bus;
dout <= reg ;
end;
