whats wrong with this code???

[Vineeth V]

library IEEE;
use IEEE.std_logic_1164.all;
entity test is
port (
a: inout STD_LOGIC_VECTOR(19 downto 0):="00000000000000000000";
clk:in STD_LOGIC
);
end test;
architecture test of test is
signal si:STD_LOGIC;
begin
process(clk)
begin
if(rising_edge(clk))then
si <= a(19);
a(19 downto 1)<= a(18 downto 0); --gave a=AB480h
end if;
end process;
end test;



I EXPECTED TO GET THE BITS IN 'a' IN 'si' ONE BY ONE DURING EACH
CLOCK ..BUT WHAT I GOT WAS A '1' ALL THE TIME....PLS HELP ME OUT

 

[Mike Treseler]

Vineeth V wrote:
Re: whats wrong with this code???

library IEEE;
use IEEE.std_logic_1164.all;
entity test is
port (
a: inout STD_LOGIC_VECTOR(19 downto 0):="00000000000000000000";
clk:in STD_LOGIC
);
end test;

No direction controls for the inout port.
Have a look at this example.
http://home.comcast.net/~mike_treseler/oe_demo.vhd

-- Mike Treseler

 

[R Quijano]

Hi

It's that u haven't declared the si as and output signal, also you can
put your declaration but it's better to put a value to the last
signal.


library ieee;
use ieee.std_logic_1164.all;
entity test is
port (
a: inout std_logic_vector(19 downto
0):="00000000000000000000";
si: out std_logic; --declaration of the serial input
clk:in std_logic
);
end test;
architecture test of test is
begin
process(clk)
begin
if(rising_edge(clk))then
si <= a(19);
a<= a(18 downto 0)&'0';
end if;
end process;
end test;