S
Shannon
This seems trivial. I'm clearly missing something very basic. Here
is the code:
process(reset, clk) is
begin
if(reset = '1') then
output <= FALSE;
elsif(rising_edge(clk)) then
if set = '0' then
output <= TRUE;
elsif trig <= '1' then
output <= FALSE;
end if;
end if;
end process;
What I expected this to produce was a type of priority mux feeding a
flip-flop. If set is '0' then output goes true (i.e highest
priority). If set is anything else then we check trig (i.e lower
priority). If trig is '1' then output goes false. Any other
conditions output should hold it's state.
The code produces the required flip-flop but completely ignores the
trig signal. The only signal feeding the input to the flip-flop is
set. I'm missing something fundamental here. Please help.
is the code:
process(reset, clk) is
begin
if(reset = '1') then
output <= FALSE;
elsif(rising_edge(clk)) then
if set = '0' then
output <= TRUE;
elsif trig <= '1' then
output <= FALSE;
end if;
end if;
end process;
What I expected this to produce was a type of priority mux feeding a
flip-flop. If set is '0' then output goes true (i.e highest
priority). If set is anything else then we check trig (i.e lower
priority). If trig is '1' then output goes false. Any other
conditions output should hold it's state.
The code produces the required flip-flop but completely ignores the
trig signal. The only signal feeding the input to the flip-flop is
set. I'm missing something fundamental here. Please help.