V
vu_5421
Hello all,
I am currently running Synplify Pro w/ Xilinx 8.1 ISE for P&R.
During mapping I get the following warning:
Checking timing specifications ...
WARNING:XdmHelpers:662 - Period specification "TS_FPGA_CLK" references
the TNM
group "FPGA_CLK", which contains both pads and synchronous elements.
The
timing analyzer will ignore the pads for this specification. You
might want
to use a qualifier (e.g. "FFS") on the TNM property to remove the
pads from
this group.
My UCF file contains the following for a 33MHZ system clock:
CONFIG STEPPING="1";
NET "FPGA_CLK" TNM_NET = "FPGA_CLK";
TIMESPEC "TS_FPGA_CLK" = PERIOD "FPGA_CLK" 30.3 ns HIGH 50 %;
I am not really sure how I would correct this, or even what the problem
is. Is it absolutely necessary to specify a PAD to PAD / PAD to FF
timespec? Is that why I am getting this warning?
Thanks any comments.
I am currently running Synplify Pro w/ Xilinx 8.1 ISE for P&R.
During mapping I get the following warning:
Checking timing specifications ...
WARNING:XdmHelpers:662 - Period specification "TS_FPGA_CLK" references
the TNM
group "FPGA_CLK", which contains both pads and synchronous elements.
The
timing analyzer will ignore the pads for this specification. You
might want
to use a qualifier (e.g. "FFS") on the TNM property to remove the
pads from
this group.
My UCF file contains the following for a 33MHZ system clock:
CONFIG STEPPING="1";
NET "FPGA_CLK" TNM_NET = "FPGA_CLK";
TIMESPEC "TS_FPGA_CLK" = PERIOD "FPGA_CLK" 30.3 ns HIGH 50 %;
I am not really sure how I would correct this, or even what the problem
is. Is it absolutely necessary to specify a PAD to PAD / PAD to FF
timespec? Is that why I am getting this warning?
Thanks any comments.