Xilinx Coregen (FFT): Unconected output pin/no driver

[Norbert Stuhrmann]

Hi,

I try to use the FFT core produced by Xilinx Corgen (module name:
fft_64). In simulation everything seems to be alright, but if I try
to create a bit file (xst->ngdbuild->map->par->bitgen), I get the
following:

WARNING:NgdBuild:440 - FF primitive 'FFT/blk00000111' has
unconnected output pin
WARNING:NgdBuild:440 - FF primitive 'FFT/blk00000114' has
unconnected output pin
WARNING:NgdBuild:440 - FF primitive 'FFT/blk00000166' has
unconnected output pin
[...]
WARNING:NgdBuild:452 - logical net 'FFT/blk00000003/sig000029c1' has
no driver
WARNING:NgdBuild:452 - logical net 'FFT/blk00000003/sig000029c2' has
no driver
[...]
bitgen -w test_fft
[...]
ERRORhysDesignRules:10 - The network <FFT/blk00000003/sig000029c2>
is completely unrouted.
ERRORhysDesignRules:10 - The network <FFT/blk00000003/sig000029c1>
is completely unrouted.

After that, the compilation stops. If I search for e.g.
blk00000003_sig000029c1 in fft_64.vhd I find it only connected to
the input of a LUT, to nothing else.

My code is attached, I'm using the Xilinx tools from the command line.

Do you have any hints?

Regards,

Norbert



library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity test_fft is
generic(
adder_width : positive := 24;
adder_depth : positive := 2;
adc_data_width : positive := 12;
window_ram_adr_width : positive := 8;
window_ram_data_width : positive := 12;
wola_num_blocks : positive := 4
);
port (
CLK, RST : in std_logic;
FFT_XK_RE : out std_logic_vector(30 downto 0);
FFT_XK_IM : out std_logic_vector(30 downto 0);
ADC_DATA: in std_logic_vector(23 downto 0)
);
end test_fft;


architecture Behavioral of test_fft is
component fft_64
port (
xn_re: IN std_logic_VECTOR(23 downto 0);
xn_im: IN std_logic_VECTOR(23 downto 0);
start: IN std_logic;
nfft: IN std_logic_VECTOR(4 downto 0);
nfft_we: IN std_logic;
fwd_inv: IN std_logic;
fwd_inv_we: IN std_logic;
sclr: IN std_logic;
ce: IN std_logic;
clk: IN std_logic;
xk_re: OUT std_logic_VECTOR(30 downto 0);
xk_im: OUT std_logic_VECTOR(30 downto 0);
xn_index: OUT std_logic_VECTOR(5 downto 0);
xk_index: OUT std_logic_VECTOR(5 downto 0);
rfd: OUT std_logic;
busy: OUT std_logic;
dv: OUT std_logic;
edone: OUT std_logic;
done: OUT std_logic);
end component;

-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of fft_64: component is "true";

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fft_64: component is true;


begin
FFT: fft_64
port map (
xn_re => ADC_DATA,
xn_im => ADC_DATA,
start => '1',
nfft => "00110",
nfft_we => '0',
fwd_inv => '0',
fwd_inv_we => '0',
sclr => '0',
ce => '1',
clk => CLK,
xk_re => FFT_XK_RE,
xk_im => FFT_XK_IM,
xn_index => open,
xk_index => open,
rfd => open,
busy => open,
dv => open,
edone => open,
done => open);

end Behavioral;

 

[Norbert Stuhrmann]

FFT core produced by Xilinx Corgen

ISE 8.1i, FFT core Version 3.2