hi all!
I hope you can help me with this bug xilinx is giving me
i'm trying to load 8 bits words from a file and store them in a variable, creating a classic rom
however Xilinx ISE webPack 9.2 is printing out
ERROR:Xst:1914 - "rom.vhd" line32: File <rom_file> does not exist.
but the file exists, and it's in the same folder of all vhd files!
can you give me a hand?
here's the code:
thanks a lot for any possible help!
TanukiChu
I hope you can help me with this bug xilinx is giving me
i'm trying to load 8 bits words from a file and store them in a variable, creating a classic rom
however Xilinx ISE webPack 9.2 is printing out
ERROR:Xst:1914 - "rom.vhd" line32: File <rom_file> does not exist.
but the file exists, and it's in the same folder of all vhd files!
can you give me a hand?
here's the code:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity ROM is
generic ( N_DATA : natural := 32;
N_ROWS : natural := 48;
N_COLS : natural := 8 );
port( rst : in std_logic;
address : in STD_LOGIC_VECTOR (N_DATA-1 downto 0);
Instruction : out STD_LOGIC_VECTOR (N_DATA-1 downto 0)
);
end ROM;
architecture Behav32 of ROM is
type Rom_Array is array (0 to N_ROWS-1) of std_logic_vector(N_COLS-1 downto 0);
signal content : Rom_Array;
begin
FILL_IN_MEM: process (rst,address)
file rom_file : TEXT open READ_MODE is "rom.txt";
variable file_line : line;
variable index : integer := 0;
variable data_tmp : std_logic_vector (N_COLS-1 downto 0);
begin
if rst = '1' then
--file_open(rom_file,"rom.txt",READ_MODE);
while (not endfile(rom_file)) loop
readline(rom_file,file_line);
hread(file_line,data_tmp);
content(index) <= data_tmp;
index := index + 1;
end loop;
else
index := to_integer(unsigned(address));
Instruction <= content(index) & content(index+1) & content(index+2) & content(index+3);
end if;
end process;
end Behav32;
thanks a lot for any possible help!
TanukiChu