Xilinx synthesis problem

[Christian Gelinek]

Hi there,

I created a CPLD design which works perfect in simulation, but does not work
in hardware. There are many warnings from the Xilinx ISE looking like

WARNING:Xst:1291 - FF/Latch <Sig> is unconnected in block <Blck>.

and

WARNING:Xst:1710 - FF/Latch <Sig> (without init value) is constant in block
<Blck>.

These come up only in the Low Level Synthesis processing step. There is one
relevant solution record on the Xilinx website (see
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18396)
with the following suggestion:
created, but the output is never connected or the signals or logic it drives
have been trimmed. Check the XST log for messages such as the following to
find signals that have been trimmed out of the design:

"WARNING:Xst:646 - Signal <my_sig> is assigned but never used." <<

However, there are no such warnings in my XST log.

Any help would be appreciated.

Christian

 

[Praveen]

Christian,

I have never encountered the same problem..but did face some problems
because of the optimization that the tool does. Did you turn off the
flags that say optimize the design? I dont know if it is a fix..but
there is nothing wrong in trying it (if you havent already done so)

-Praveen.

 

[Christian Gelinek]

Praveen,

the problem is gone after upgrading my ISE from 6.1 i to 7.1 i with service
pack 1 and patch 21168. It seems to me that there was a bug in the optimizer
of the old ISE version. Now the design is about twice as big and so does not
fit into the CPLD anymore. I think, that the optimizer of the old version
trimmed some of the logic and therefore was able to shrink the design so it
fitted into my CPLD. But because this removal was illegal, the design did
not work properly.

Best regards
Christian

 

[sandeepv]

Synthesis problem

Hi all,
I have worked on a design and i did syntax check which gives no errors. But when i tried to synthesis it, i am unable to synthesize the circuit even after 26 hours. It just showing that synthesis is running. It is stopping at hirarchy check level.
If any of you can give me a solution it would be appreciable.
Thanks
Sandeep