yet again on dual edge!

[tanukichu]

hello!
i hope someone can help us in a nasty problem we've found in a vhdl homework

we have to desaign a register file which reads from register on the rising edge of the clock and writes to (possibly) other register on the falling edge.

we tried this simplistic approach

entity Register_File is
port(
   clock : in std_logic;
   reset : in std_logic;
   port_S_addr: in register_address;
   port_T_addr: in register_address;
   port_D_addr: in register_address;
   write_D_EN: in std_logic;
   port_D_IN : in std_logic_vector (N-1 downto 0);    --content to be written
   port_S_OUT: out std_logic_vector (N-1 downto 0);  --content to be read
   port_T_OUT: out std_logic_vector (N-1 downto 0);  --content to be read
   output_dep: out std_logic
);
end Register_File;

architecture Behavioral of Register_File is
signal reg : register_array;
begin

   process (clock,reset)
   begin
       if reset = '1'
       then
           for i in 0 to N_REGS-1 loop
               reg(i) <= (others => '0');
           end loop;
       elsif clock'event and clock = '1'
       then
           --reading stuff
           port_S_OUT <= reg(port_S_addr);    --first register
           port_T_OUT <= reg(port_T_addr);    --second register
       elsif clock'event and clock = '0'
       then
           --writing stuff
           reg(port_D_addr) <= port_D_IN;    --destination register
       end if;
   end process;

end Behavioral;

but then we discovered to our despair that it is not possible to syntesize double edge circuits!
As a matter of fact xilinx gives "Signal reg<1> cannot be synthetized, bad synchronous description".

do you have any slight idea which may help us??
thanks you in advance to everyone!!!

 

[jeppe]

A short and hopefully precise answer:

You can always read from a register - make a separate process to read and clock the data "port_S_OUT" and "port_T_OUT".

Delete the reading stuff from the posted process and the problem should be solved.

entity Register_File is
port(
   clock : in std_logic;
   reset : in std_logic;
   port_S_addr: in register_address;
   port_T_addr: in register_address;
   port_D_addr: in register_address;
   write_D_EN: in std_logic;
   port_D_IN : in std_logic_vector (N-1 downto 0);    --content to be written
   port_S_OUT: out std_logic_vector (N-1 downto 0);  --content to be read
   port_T_OUT: out std_logic_vector (N-1 downto 0);  --content to be read
   output_dep: out std_logic
);
end Register_File;

architecture Behavioral of Register_File is
signal reg : register_array;
begin

   process (clock,reset)
   begin
       if reset = '1'
       then
           for i in 0 to N_REGS-1 loop
               reg(i) <= (others => '0');
           end loop;
       elsif clock'event and clock = '0'
       then
           --writing stuff
           reg(port_D_addr) <= port_D_IN;    --destination register
       end if;
   end process;
  
   process( Clock)
   begin
       if clock'event and clock = '1'
       then
           --reading stuff
           port_S_OUT <= reg(port_S_addr);    --first register
           port_T_OUT <= reg(port_T_addr);    --second register
       end if;
    end process;
end Behavioral;

Your welcome
Jeppe

 

[tanukichu]

well it synthetized all the way!!!

thanks a lot )))))