VHDL

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comp.lang.vhdl
H
C lines To VHDL
  • hailconan
Replies
3
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699
ALuPin
A
J
exiting from state machine
  • jiten
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3
Views
972
Alex
A
S
warning when using design compiler
  • sravan reddy
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0
Views
853
sravan reddy
S
S
VHDL-AMS MOS Level3
  • Stefan Klein
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0
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1K
Stefan Klein
S
D
VHDL200x- Fixed Point Problem in Quartus 5.0
  • Divyang M
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6
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1K
Divyang M
D
C
[Q] transaction
  • csosz33
Replies
0
Views
973
csosz33
C
W
Which is faster in ASIC: 2-input AND gate or a 2-input multiplexer
  • Weng Tianxiang
Replies
12
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3K
Neo
N
U
ROM
  • u_stadler
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5
Views
1K
mk
M
J
problem with timing simulation
  • JEmoderatz
Replies
5
Views
1K
Ralf Hildebrandt
R
S
Maximum clock frequency ?
  • Skybuck Flying
2
Replies
20
Views
7K
Colonel Forbin
C
N
Vector Slicing in assigments
  • nrivera.eng
Replies
5
Views
881
Zara
Z
E
Convert from std_logic_vector to real
  • eNo
Replies
2
Views
38K
Hubble
H
D
Synthesizing high-density designs in Quartus
  • Divyang M
Replies
4
Views
1K
Divyang M
D
B
I thought that this code compiled, now it does not?
  • Bob
Replies
1
Views
5K
Ralf Hildebrandt
R
K
ModelSim control
  • Kev P. (AKA Niv)
Replies
6
Views
6K
Kev P. (AKA Niv)
K
S
What's the best IDE for VHDL so far ? ;)
  • Skybuck Flying
Replies
3
Views
4K
Andy Peters
A
S
problem with modelsim
  • sravan reddy
Replies
4
Views
852
sravan reddy
S
U
ModelSim Error
  • u_stadler
Replies
2
Views
3K
Andy Peters
A
U
avoid latches
  • u_stadler
Replies
2
Views
2K
Hubble
H
J
ANN: Zeus Version 3.95 Editor Released
  • Jussi Jumppanen
Replies
0
Views
998
Jussi Jumppanen
J
B
Synchronising Reset APP Note
  • Benjamin Todd
Replies
2
Views
881
Benjamin Todd
B
B
Dilemna w/ generic port of type array of slv
  • Brandon
Replies
5
Views
2K
combinational.logic $ soc-ip.com
C
S
Problem in synthesizing function
  • sps
Replies
1
Views
1K
Ralf Hildebrandt
R
U
error in code?
  • u_stadler
Replies
5
Views
889
Ralf Hildebrandt
R
S
file lines reading
  • srinukasam
Replies
0
Views
967
srinukasam
S
T
Is it possible to define an alias of a type?
  • TigerJade
Replies
4
Views
906
Jonathan Bromley
J
W
Multiplexer Index
  • woko
Replies
2
Views
1K
woko
W
A
Synchronous Serial Port design
  • adriana
Replies
6
Views
5K
Ralf Hildebrandt
R
?
what's incorrect ALIAS
  • =?ISO-8859-15?Q?Stefan_Schw=E4rzler?=
Replies
1
Views
853
Jonathan Bromley
J
K
How do intel/amd design their processors ?
  • keith
Replies
7
Views
11K
Clifford Heath
C
B
Legality of type conversion on instance ports?
  • Brandon
Replies
1
Views
945
Jim Lewis
J
S
sim_file reading
  • srinukasam
Replies
1
Views
794
coshzz
C
T
assigning delays for bidirectional signals
  • Tom
Replies
4
Views
3K
Ralf Hildebrandt
R
S
Question about 2 bit counter example.
  • Skybuck Flying
Replies
3
Views
8K
Ralf Hildebrandt
R
B
Bulletproofing CPLD Design
  • Benjamin Todd
Replies
7
Views
1K
Benjamin Todd
B
P
Wait statement
  • Peter
Replies
6
Views
7K
Jonathan Bromley
J
T
Simulating testbench waveform error: "No feasible entries for subprogram write"
  • Taras_96
Replies
2
Views
7K
Taras_96
T
R
generic record exploration.
  • Rick North
Replies
3
Views
1K
Jim Lewis
J
M
VHDL 200X....when?
  • My Name
Replies
3
Views
972
Jim Lewis
J
T
N-input AND gate
  • TigerJade
Replies
9
Views
2K
Jos De Laender
J
S
a pipeline with collision detection
  • skatoulas
Replies
3
Views
1K
skatoulas
S
L
Overflow detector
  • Lilmiss
Replies
1
Views
3K
Ralf Hildebrandt
R
B
User-defined global library in ModelSim 6.0?
  • Brandon
Replies
2
Views
1K
Brandon
B
S
Ok cpu designed now what ? ;)
  • Skybuck Flying
Replies
1
Views
1K
Martin Thompson
M
S
Main memory <-> Cpu communication ?
  • Skybuck Flying
Replies
2
Views
2K
Jonathan Kirwan
J
G
Instantiate primitives in for-generate?
  • George Mercury
Replies
2
Views
1K
jtw
J
S
ANN: Project VeriPage Announces New SystemVerilog Article
  • Swapnajit Mittra
Replies
0
Views
1K
Swapnajit Mittra
S
K
Keyboard Interface With Handshake
  • Keyvan Jamaleddin
Replies
0
Views
2K
Keyvan Jamaleddin
K
E
un-intentional gated clock after synthesis
  • Elinore
Replies
8
Views
2K
Andy Peters
A
A
Conditional compilation in VHDL
  • avishay
Replies
4
Views
4K
Andy Peters
A

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