VHDL

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comp.lang.vhdl
R
What are these files?
  • robboll
Replies
4
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849
Neo
N
K
Synopsys Design Analyzer in command prompt
  • Kenneth Brun Nielsen
Replies
6
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4K
Kenneth Brun Nielsen
K
K
Case choice must be a locally static expression.
  • Kenneth Johansson
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9
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14K
Mike Treseler
M
J
Gezocht: Ervaren VHDL programmeur
  • Jeroen de Zoeten
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0
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2K
Jeroen de Zoeten
J
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Linking problem in Primetime
  • tinoosh
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1
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1K
topgun
T
T
Variable 'variable lengths'
  • Taras_96
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2
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1K
Taras_96
T
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INFO:Xst:1304 -- precise definition anyone?
  • Joseph
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2
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1K
Ben Twijnstra
B
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pulse streatcher
  • Praveen
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2
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1K
Ralf Hildebrandt
R
T
latches again
  • Tomas
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1
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1K
Ralf Hildebrandt
R
A
Sync + FIFO
  • ALuPin
2
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36
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4K
Ronald H. Nicholson Jr.
R
M
extension pack
  • My Name
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0
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1K
My Name
M
A
Latches problem
  • aaaaaa
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2
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1K
Jim George
J
B
can 2 if's to 1 if save 1 clock cycle?
  • bxbxb3
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2
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827
Jim George
J
V
Problem in array formation
  • vedpsingh
Replies
0
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794
vedpsingh
V
S
cf_fft
  • shgjoker
Replies
2
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1K
info_
I
I
Case statement illusions ?
  • info_
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13
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2K
info_
I
A
Signal use from pin
  • ALuPin
Replies
2
Views
997
ALuPin
A
C
Generic, synthesizable synchronous 16x32 FIFO
  • Calvin
Replies
1
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1K
Neo
N
S
An easy question for everyone
  • Simon.Tiplady
Replies
2
Views
914
Ralf Hildebrandt
R
D
dynamic size of ports
  • Dan Nilsen
Replies
9
Views
996
backhus
B
M
Register Files for synthesis
  • Mohammed A khader
Replies
1
Views
1K
Mohammed A khader
M
R
Flip Flop vs Registers
  • Robert Chandler
Replies
6
Views
22K
Ralf Hildebrandt
R
D
Interfacing Digital Camera
  • Deepa
Replies
6
Views
3K
info_
I
M
error "choice must be discrete range" with CASE
  • Manfred Balik
Replies
3
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11K
Brian Drummond
B
N
post translate simulation
  • Nisheeth
Replies
2
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2K
Mike Treseler
M
L
*RANT* Ridiculous EDA software "user license agreements"?
  • license_rant_master
2
Replies
37
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3K
marcus.harnisch
M
N
Variable to signal assignment
  • Nicolas Matringe
Replies
2
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12K
Mike Treseler
M
T
Generic in CASE choice ?!?
  • Thorsten Bunte
Replies
4
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1K
Taras_96
T
P
Testing and finding the error in my design (THINK it's in the presampler/ringbuffer)
  • Preben Holm
Replies
2
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1K
Preben Holm
P
M
PCI plug n play and Graphics card implementation
  • mansoor.naseer
Replies
6
Views
4K
Andy Peters
A
N
Converting synthesized VHDL/Verilog to spice netlist
  • Noohul Ali
Replies
2
Views
4K
Neo
N
B
How to instantiate identical components by for loop or generate in VHDL?
  • boku
Replies
2
Views
26K
David R Brooks
D
A
Creating RAM in VHDL as Project
  • Avatar7
Replies
1
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7K
thomas
T
A
Bug in DDR template in Lattice FPGAs ?
  • ALuPin
Replies
8
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2K
ALuPin
A
M
Synplify warning CL209
  • Mohammed A Khader
Replies
4
Views
2K
Ken McElvain
K
B
gtkwave is back online, current win32 binaries available
  • bybell
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2
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2K
bybell
B
R
searching for reuse database and archive software
  • Rainer
Replies
3
Views
982
Swapnajit Mittra
S
T
Free VHDL Analysis Tool (vhdlarch 0.1.0)
  • tom
Replies
4
Views
3K
Mike Treseler
M
P
Simulation and realworld problem in design - what is wrong?
  • Preben Holm
Replies
6
Views
1K
Mike Treseler
M
X
multiplier with one fixed value other user defined
  • xiibweb
Replies
6
Views
1K
Mohammed A khader
M
D
Asynchronous Design
  • dutchgoldtony
Replies
3
Views
849
charles.elias
C
P
fundamental question on process
  • Praveen
Replies
3
Views
1K
Praveen
P
S
ANN: PSL and DPI articles on Project VeriPage
  • Swapnajit Mittra
Replies
0
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1K
Swapnajit Mittra
S
M
cf FFT
  • Marco
Replies
2
Views
2K
info_
I
M
Ambigous operator '&'
  • Mohammed A khader
Replies
8
Views
2K
Mike Treseler
M
J
A question about syntax of VHDL
  • Jim Huang
Replies
6
Views
11K
info_
I
X
multiplier one fixed value other user defined
  • xiibweb
Replies
1
Views
890
Ralf Hildebrandt
R
K
Can real number be synthesized
  • Kuan Zhou
Replies
2
Views
1K
Phil Tomson
P
D
Design Configuration
  • Divyang M
Replies
2
Views
774
Divyang M
D
A
Some signals became ? and missing on the simvision, why?
  • Acceed See
Replies
1
Views
1K
Carl W.
C

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