VHDL

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comp.lang.vhdl
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Question on asynchronous or handshake circuits
  • rajan
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1
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921
Kai Harrekilde-Petersen
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Topweaver 3.0!Free powerful GUI HDL structural integration tool.
  • Topweaver
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0
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3K
Topweaver
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Good Verilog & VHDL reference books
  • hdl_book_seller
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1
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4K
Amontec, Larry
A
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Signal Attribute Issue
  • Calvin
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2
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847
Milos
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VHDL model of a push button debouncer
  • fpgawizz
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4
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14K
Winfried Salomon
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Simple question
  • VHDL_lover
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2
Views
648
VHDL_lover
V
E
Good book for synthesis?
  • Eric
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2
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897
Mike Treseler
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problem with loop statement
  • bxbxb3
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8
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2K
Peter Hermansson
P
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Comparision
  • john
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2
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947
Mike Treseler
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FSM IOB problem
  • Eric
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3
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1K
aa55
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Procedures and array element assigment from different processes.
  • Seb
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12
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1K
Mike Treseler
M
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rtl_attributes
  • Mohammed A khader
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3
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1K
Mohammed A khader
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VHDL register file synthesis
  • stoyan.shopov
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3
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16K
stoyan.shopov
S
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EDPS 2005 Early Registration Ends March 16, 2005
  • b_kapoor
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0
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1K
b_kapoor
B
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State Machine prblem in VHDL
  • fpgawizz
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8
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3K
fpgawizz
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Calling netlist module in a design
  • williams
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2
Views
830
Mohammed A khader
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Global Reset paths
  • =?ISO-8859-1?Q?Andr=E9s?=
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11
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3K
A Beaujean
A
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CA - DFT Manager Position Available
  • stuart
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0
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1K
stuart
S
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Synplify to Quartus IO standard
  • Pierre-Louis
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3
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1K
Mike Treseler
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Clock Divider
  • Mohammed A khader
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4
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22K
charles.elias
C
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using RS232 port to send data to a spartan 3 board
  • fpgawizz
Replies
5
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6K
dutchgoldtony
D
A
Coding style for CPLD vs FPGA
  • Analog Guy
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3
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6K
Klaus Falser
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A
NC Verilog and specify block query
  • Anshul Bansal
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1
Views
3K
Paul Uiterlinden
P
B
maximum clock speed so that a design can safely operate
  • benn
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2
Views
1K
Neo
N
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making a glitch filter
  • rajan
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2
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14K
Ulf Samuelsson
U
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DPIMREF Instability
  • dutchgoldtony
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0
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1K
dutchgoldtony
D
A
Over-Sampling
  • ALuPin
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5
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2K
jtw
J
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feasibility of stochastic systems on FPGA
  • Divyang M
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1
Views
995
Divyang M
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build a simple cpu
  • LIMITSTATE
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4
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11K
Pablo Bleyer Kocik
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D
Call for FPGAworld 2005
  • David Kallberg
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0
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753
David Kallberg
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signal update problem
  • Kuan Zhou
Replies
1
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804
Egbert Molenkamp
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compteur VHDL
  • Martial DOERPER
Replies
3
Views
5K
bxbxb3
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Pin declarations in EC/ECP FPGAs
  • =?ISO-8859-1?Q?Andr=E9s?=
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11
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4K
cristian
C
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state machine sync process
  • Andrei Bejenari
Replies
4
Views
971
Mike Treseler
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lpm_counter instead adders
  • Dan NITA
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4
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2K
Dan NITA
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mux:6 input signals
  • rajan
Replies
2
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899
Neo
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Help!!!!!!!!!!!!!!!
  • De.Phoenix
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3
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1K
Kasper
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ORing of the 2 bit vector with 1 bit
  • rajan
Replies
2
Views
3K
dutchgoldtony
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Avoiding "Bad Synchronous Description" Error when Synthesizing
  • Takuon Soho
Replies
5
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2K
Charles Bailey
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Call for Papers: 2005 MAPLD International Conference
  • Richard B. Katz
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0
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926
Richard B. Katz
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ISE 6.3i error : unable to find flow prefix
  • Nisheeth
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0
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1K
Nisheeth
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RISC model
  • =?ISO-8859-1?Q?Joaqu=EDn_Gracia?=
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4
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1K
=?ISO-8859-1?Q?Joaqu=EDn_Gracia?=
?
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making a time filter
  • rajan
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1
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906
Mike Treseler
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switching between Altera and Xilinx
  • bobrics
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5
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3K
bobrics
B
C
generating within a case statement
  • colin
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3
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1K
colin_toogood
C
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Indexing the bits of an Integer?
  • Takuon Soho
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6
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1K
Takuon Soho
T
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VHDL -- Some sort of array of std_logic_vectors ?
  • springer54
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8
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6K
springer54
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A
[ICSEng'05] Final CFP - due date March 10, 2005
  • avinash
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0
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986
avinash
A
A
[ICCIMA'05] Final Call for Papers; Due Date March 10, 2005
  • avinash
Replies
0
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929
avinash
A
F
bad synchronous description error
  • fpgawizz
Replies
4
Views
2K
dutchgoldtony
D

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