VHDL

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comp.lang.vhdl
B
How To...Symbiol from HDL file?
  • buke2
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2
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847
buke2
B
E
Behavioural VHDL and Synthesis Tools
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0
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948
Edmond Cote
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R
Back Annotation simulations
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4
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6K
Ansgar Bambynek
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tri-state buffer with Xilinx ECS
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1
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4K
Weng Tianxiang
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Modelsim behavior
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1
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2K
Jonathan Bromley
J
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sinus generation
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1
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8K
Jonathan Bromley
J
M
white noise generator
  • MNQ
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5
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6K
MNQ
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USB vhdl code (followup)
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3
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4K
Alex Gibson
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Question: Writing text file based TestBenches vs. Waveform file based simulation.
  • BLF
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4
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2K
Mike Treseler
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Re-taking VHDL class and need help.
  • mugz
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11
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1K
HDL Book Seller
H
H
Bone up on VHDL & Verilog with these great reference texts at 60% off Amazon
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0
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1K
HDL Book Seller
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4
WANTED: Embedded software developers
  • 4csjobs
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0
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711
4csjobs
4
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generic question
  • The Weiss Family
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2
Views
849
Jim Lewis
J
S
Port map with combining
  • Sylvain Munaut
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2
Views
767
Sylvain Munaut
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help with modelsim error (delay in signal assignment must be ascending)
  • ra
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3
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8K
Egbert Molenkamp
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How to start (newbie)
  • e7
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12
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1K
Ken Smith
K
C
SRL and ROL
  • Chris Connelly
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3
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20K
Mike Treseler
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post PAR simulation with Xilinx Project Navigator: how?
  • ra
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0
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2K
ra
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U
set tri-state
  • Urban Stadler
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1
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1K
Peter Hermansson
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D
Modification of Duty Cycle - Possible?
  • Drew
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2
Views
2K
Charles M. Elias
C
S
Determine entity/component port signal range
  • Sven Heithecker
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2
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1K
Ralf Hildebrandt
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?
determining of the position of the MSB
  • =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=
2
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20
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13K
Jonathan Bromley
J
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modified booth or mux based (Pekmestzi) multiplier
  • transformer
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1
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4K
Lorenzo Di Gregorio
L
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rtl
  • teamgda
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5
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2K
Ken Smith
K
I
Free vhdl tool?
  • Ingo Rose
Replies
7
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4K
Ken Smith
K
P
vhdl and math_ieee
  • Patrice
Replies
1
Views
876
Jim Lewis
J
D
Virtual Computer Corporation (VCC) Virtual Workbench VW300
  • Derek Simmons
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0
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1K
Derek Simmons
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Verilog (include) to VHDL (....) problem
  • Luc
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6
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7K
Jim Lewis
J
S
Personnal type as port
  • Sylvain Munaut
Replies
1
Views
718
Allan Herriman
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Openings in ASIC_Embedded In World's Top 3 Chip Company_Bangalore_India
  • GSK1976
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0
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872
GSK1976
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Synopsys Presto VHDL
  • Tom Verbeure
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1
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2K
Wallclimber
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Call for Papers: ASYNC-2005 (New York City)
  • Montek Singh
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0
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1K
Montek Singh
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Mixed VHDL/Verilog + defparam
  • Hans
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1
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11K
Hans
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Max Min
  • Patrick
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1
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4K
Jonathan Bromley
J
S
Modeling tools for State machines...
  • Stefan Oedenkoven
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2
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1K
Stefan Oedenkoven
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P
quartus and files i/o
  • PATRICE
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0
Views
741
PATRICE
P
A
Choosing PLL
  • ALuPin
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1
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1K
Subroto Datta
S
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Simulation initialization problem
  • Tomek
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8
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1K
Tomek
T
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kinda "overloading"
  • MM
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1
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835
Jonathan Bromley
J
M
write only bits in registers
  • MM
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3
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1K
Ralf Hildebrandt
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bnary files
  • PATRICE
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1
Views
861
Jonathan Bromley
J
B
VHDL and extracing equations
  • buke2
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2
Views
898
buke2
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huge fsm
  • Mai
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4
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1K
J. op den Brouw
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library XilixCoreLib cannot be found
  • ra
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0
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2K
ra
R
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Is it possible to impliment Blockram with a reset?
  • RaymondCaleatry
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1
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2K
Tim Hubberstey
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shared graphics in notebook
  • suz
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6
Views
6K
Jason Zheng
J
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Simulating Bidirectional Pins - How is it displayed?
  • Drew
Replies
1
Views
996
wieli1
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edif2blif
  • Fabio
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0
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1K
Fabio
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simulation problem
  • Urban Stadler
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1
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2K
Tim Hubberstey
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ModelSim RGB Singal -> Image ?
  • Michael Schmid
Replies
1
Views
1K
Frank Buss
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