VHDL

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comp.lang.vhdl
J
About 1076.6-2004
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0
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917
Just an Illusion
J
D
interconnecting two same type of components
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854
Just an Illusion
J
M
Changing generics in top-level module
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Just an Illusion
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A
Modelsim Waveform
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signed signal assignment
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P
signed to unsigned
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Bus reduction
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Returning multiple variables
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2
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793
Allan Herriman
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C
Problem with signal drivers
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Don Golding
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C
OLD Spartan xcs10 with xilinx 6.2i ??
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1
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Leon Heller
L
C
One-hot Coding of State machines
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Wallclimber
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J
Bangalore-based ASIC/CAD Tech Lead, Parasitic Extraction
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2
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salman sheikh
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What's the VHDL programmer's profile?
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3
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Micru
M
R
state-machine
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0
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846
Runar Gjelsvik
R
R
MAPLD 2004: Registration Open and Program Announced
  • Richard B. Katz
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0
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893
Richard B. Katz
R
M
Drivers in subprograms
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4
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890
MM
M
A
Developing testbenches with ISE & Modelsim
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AndyAtHome
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Simulating VHDL design with ModelSim
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Marcus Harnisch
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M
RAM initialization
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1
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Mike Treseler
M
V
Bangalore-based SoC Wireless Design Manager
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788
Vamsi
V
R
HELP!!!! Newsgroup not updating....
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0
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768
Rory
R
A
USB vhdl code
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4
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15K
Fabio G.
F
F
How to compute 2^N in VHDL?
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3
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Fabio G.
F
P
USB vhdl code
  • Paolo Santinelli
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0
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1K
Paolo Santinelli
P
M
Adding elements of an array
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4
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1K
Christoph M. Wintersteiger
C
J
Bangalore-based SoC Wireless Design Manager
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1
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999
me tew!
M
S
conversion
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6
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1K
Ray Andraka
R
P
Glitchs at the output of a latch
  • Patrick
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5
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1K
Thomas Stanka
T
H
Looking for top Verilog, VHDL reference texts?
  • HDL Book Seller
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0
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1K
HDL Book Seller
H
R
RS-232
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1
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2K
Thomas Reinemann
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A
SRT DIvision, Square root and reciprocal square root
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2K
alghazo
A
P
newby: eliminating excess flipflops from simple state machine
  • Paul Guy
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3
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1K
Paul Guy
P
N
VHDL code to light up LED???
  • network lines
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8
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11K
Symon
S
W
Scope interpretation - Bug in ModelTech?
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3
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1K
Wallclimber
W
J
VHDL book for sale
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0
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753
JingleBEV
J
D
multisourcing problem
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5
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2K
Ray Andraka
R
A
Quartus II v3, Circuit after synthesized?
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1
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949
Mike Treseler
M
P
Library metamor ?
  • Peter Prikasky
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2
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958
Jim Lewis
J
A
ISE problem - multiplier inputs on schematic are not assigned correctly.
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1
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1K
AndyAtHome
A
J
looking for some good books
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3
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1K
VhdlCohen
V
S
Initialization
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4
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983
ivero
I
V
namespaces
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0
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970
valentin tihomirov
V
W
IC area of flip-flop and SRAM?
  • Weng Tianxiang
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1
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2K
Samuel Fuhrer
S
D
signal and varriable assignment
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2
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887
deep
D
P
Frequency divider
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6
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6K
Charles Bailey
C
M
Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench
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2
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3K
Charles Bailey
C
K
ncvhdl error
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2
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1K
kish
K
W
Best book on a flip flop circuit
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Mike Treseler
M
H
non recoginition of packages in fpga compiler 2
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1
Views
886
Charles M. Elias
C
M
Reading/writing data to/from files into 2D array
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Modukuri
M

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