Design is too large for the device! xc3s400

[Ray Andraka]

Ray, pretty clever.
But more difficult to understand, or to modify.
And what do I do with the unused port?

But nevertheless, hats off to a smart solution...
Peter

Why is it difficult to understand or modify?

It is just a counter that gets loaded with (delay-2) and then counts
down until it becomes -1, and then reloaded. The load value can be
changed at any time, and takes effect the next time the counter reaches
the terminal count of -1 (this downcounter has the advantage of not
requiring any decoding, and of having an easily adjusted modulus). The
counter output becomes the address to the memory. I think it is pretty
straightforward to comprehend, do you find it otherwise? The only
difference is just being a little clever in the counting and taking
advantage of the read before write capability of the memory.
As far as modifying it, I'm not sure I see the difficulty there
either: The modulus is easy to change, and in particular can be easily
changed dynamically. You can easily change the width of the counter for
different aspect ratios on the memory, say for instance if you wanted to
delay a 9 bit signal by a delay not to exceed 2048 clocks. Beyond that,
I'm not sure what modifications you'd want to make, or for that matter
what modifications that wouldn't be as difficult in the two port scheme
you offered.
As far as the unused port goes, you can leave it unused if you want, or
if the depth of the shift register is less than half the memory depth,
you can set the high order address bit to 0 on the shift register side
and to '1' on the spare port and then you can use the spare port side as
a 9K bit memory for anything your heart desires. Unfortunately, the
tools can't figure that out for you so you have to instantiate and
initialize (and initialize if needed) the memory. You can also use the
second side if you need a wide shift register delay, like you might use
for a digital filter.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email (e-mail address removed)
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Andy Peters]

I am trying to delay a pulse by N ticks where N takes a maximum value
of 3454...N is a variable here....

How wide is the pulse? Answer in clock ticks, please. I think we're
assuming that the pulse exactly one clock tick wide.

-a

 

[Peter Alfke]

Ray, I agree 100% with you. Sorry for the flip remark.
It's easy to change the count modulus. And the read-before-write
feature in all the newer Xilinx BlockRAMs is a real bonus.
I owe you one...
Peter Alfke

 

[methi]

Hello,

The pulse is 40 ns wide....

Thank you everybody....


Methi

 

[Andy Peters]

Hello,

The pulse is 40 ns wide....

I asked, "how wide is the pulse. In number of clock ticks."

How many clock cycles is 40 ns? The actual number in units of time is
meaningless.

-a

 

[methi]

Its one clock tick.......My clock is 27Mhz.....

Thanks

 

[Peter Alfke]

Methi, you have received many suggestions from this group. Perhaps it
is time to tell us which ones you have tried or are going to try. It
seems to me that the original title of this thread has become
meaningless. You can fit your design many times over into the quoted
device...
Peter Alfke, Xilinx Applications

 

[methi]

Methi, you have received many suggestions from this group. Perhaps it
is time to tell us which ones you have tried or are going to try. It
seems to me that the original title of this thread has become
meaningless. You can fit your design many times over into the quoted
device...
Peter Alfke, Xilinx Applications

Thankyou everybody...for all the suggestions

I have received lots of help

I am first tryint the BlockRAM

And am also goin to try the simple counter...

Thankyou once again

Methi

 

[glen herrmannsfeldt]

Ray Andraka wrote:



(snip regarding BRAMs and shift registers)

Peter, with SPartan3, he can do it with one port of the BRAM if he uses
a modulo-N count instead of a straight 14 bit binary count. I showed
this in the code I posted earlier. The modulo N count is easy if you do
it as a loadable down-count that reloads itself when it goes negative.

So you read the previous data while writing the new data into
the same address.

-- glen

 

[glen herrmannsfeldt]

Ray Andraka wrote:

(snip)

Why is it difficult to understand or modify?

It is just a counter that gets loaded with (delay-2) and then counts
down until it becomes -1, and then reloaded. The load value can be
changed at any time, and takes effect the next time the counter reaches
the terminal count of -1 (this downcounter has the advantage of not
requiring any decoding, and of having an easily adjusted modulus). The
counter output becomes the address to the memory. I think it is pretty
straightforward to comprehend, do you find it otherwise? The only
difference is just being a little clever in the counting and taking
advantage of the read before write capability of the memory.
As far as modifying it, I'm not sure I see the difficulty there
either: The modulus is easy to change, and in particular can be easily
changed dynamically. You can easily change the width of the counter for
different aspect ratios on the memory, say for instance if you wanted to
delay a 9 bit signal by a delay not to exceed 2048 clocks. Beyond that,
I'm not sure what modifications you'd want to make, or for that matter
what modifications that wouldn't be as difficult in the two port scheme
you offered.

It would seem to perform better if you change the length while it
is running. Though at some point changing the length of a running
shift register is not so well defined, but the results in Peter's
case are a little strange.

-- glen