Design toplevel module as schematic?

[valtih1978]

I like to explain students that representation is more structural at the
higher levels of abstraction. It is because you start design at the top
level. You refine the design by implementing the components (defining
their structure). At the bottom level you have the gates. As VHDL
designer you know that components do not have the structure at the
bottom level. You describe the elementary components by behavioral
processes. Now, you understand that the top level is necessarily has
known structure. Might be this intuition is taken too far by some bigots
but the big picture of the World seems to be really useful in any case.

 

[rickman]

That was not the point, I agree that schematics are not standard in the
ASIC world, the link was to counter your *all* argument.

And that is why I say "nearly" all.

 

[Anssi Saari]

I prefer the second one, my colleague the first. The only advantage I
see for using schematic coding, is that I have a visual overview of my
toplevel modul and I quickly can find which blocks are connected
together.

But that kind of overview is usually provided by synthesis tools, no?
Quartus does, years ago when I used Precision it did it too. Can't
remember off hand if other tools can do that.

Maybe someone can give me a few impressions how you handle the
toplevel module.

Once upon a time a coworker created an automated tool to build the
toplevel or in fact the whole hierarchy. It operated on a simple config
file and some very simple rules for connecting signals. Basically if two
modules on the same level had a matching input and output those would be
connected together, otherwise the signal would be pushed up in the
hierarchy. It was for Verilog though and the IP is owned by Ericsson so
not available for general consuption. Too bad really. But automation
over tedium is my first choice.

These days, as Emacs can copy a VHDL entity and paste it as an instance
and signals it's fairly obvious what I prefer as an Emacs user. I had to
take a look at an old hybrid schematic / VHDL design recently which was
done in MaxPlus and I thought it was a filthy mess and very difficult to
figure out what connected where. Of course the readability of a
schematic depends on whoever did the schematic. I guess you could
obfuscate a VHDL toplevel too if you really wanted to.

Some years ago I was in a company where they used I think HDL
Designer. It at least generated reasonable VHDL from the visual
representation so portability wasn't an issue. OTOH, the GUI drawing
part was pretty awful. Autosave with no undo made for a pretty terrible
experience. One false move and spend hours fixing the result...

Related to this, I'd like to get the top level entity and FPGA pin list
from the schematic automagically. I had the pin list part once upon a
time and it was great. I wonder how common this is in schematic tools?
Recently I wrote a few lines of Python to convert from some kind of pin
info from PADS to Quartus pin assignments. Another time years ago some
other Mentor schematic tool could produce a UCF file for Xilinx. Very
handy as the FPGA in that project had over 1000 pins...