-- This code not for synthesize - only for simulation
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test_div is
Port ( a : out integer);
end test_div;
architecture Behavioral of test_div is
begin
a <= integer(real(1234)/1.36);
end Behavioral;
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.