Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...

[Ray Andraka]

"Shift registers can be counted as a state machine only when only one
bit is set or reset among all its bits. Otherwise it cannot be counted
as a state machine."

"I don't understand this restriction at all.

B.S. For example, a shift register can be used in a bargraph manner so
that the states are

000001
000011
000111
001111
011111
111111

This has an advantage over the one-hot shift register state machine you
described in that it has fewer terms feeding each register. That can
make a big difference in the maximum clock rate of the state machine.

 

[Weng Tianxiang]

B.S. For example, a shift register can be used in a bargraph manner so
that the states are

000001
000011
000111
001111
011111
111111

This has an advantage over the one-hot shift register state machine you
described in that it has fewer terms feeding each register. That can
make a big difference in the maximum clock rate of the state machine.

Hi Ray,
OK, thank you for your example.

Your shift register is a state machine if we define different bit
patterns appeared in your example as individual states.

I have changed my mind to accept non one-hot encoding for shift
registers based on glen's suggestion.

My state machine definition is still right without any violations with
your example.

Weng

 

[comp.arch.fpga]

Weng,

you are free to invent as many technical and mathematical constructs
as you like.
BUT: It is utterly stupid to use the same name for it as a well
established construct.

Finite State Machines are extremely well understood since decades.
http://en.wikipedia.org/wiki/Finite_state_machine

And I can assure you:
In digital electronics anything that has state is a state machine.

In general:
- State machines do not need to have a reset. There are machines that
return to the reset state
if a certain input sequence is applied. I posted links to papers about
that, which you apperently ignored.
Any FPGA around has a state machine that works without reset: The JTAG-
controller.
- Names in state machine do not need to have names.
- State machines can be combined to larger machines. These are still
state machines, but the
states are not mutual exclusive anymore.
- In complexity therory an important class of state machines are non
deterministic state machines.
These can be in mutliple states at the same time. Quantum computing
provides a real world implementation for
another type of state machines that are in multiple states at the same
time.
- While state machines with a single state are not very useful, theory
becomes a lot simpler if you still allow them to be state machines.

This means that for the well establish name "State Machine" ALL OF
YOUR ASSUMPTIONS ARE FALSE!

Please find a new name for the strange thing that you are talking
about.
And please: Listen to people, and believe them. Most of this has been
posted before and you ignored it.
You are extraordinarily stubborn.

As far as your original question goes:
A set of state memories (flip-flops, memory cells) can be more or less
arbitrarily partitiones into state machines.
The extremes beeing one machine per state bit, or one big machine for
the whole chip. Both extremes often are not useful.
What you described is a central controller updating a set of state
machines in memory. It is valid to call that a set of state
machines. But if you allow for that construct, a software
implementation of Conways game of live easily beats your example
by orders of magnitude. You have two state bits for each pixel and a
central controller updating the states of the machines.

Kolja Sulimma

 

[Weng Tianxiang]

Hi KS,
Good comments and I think it is based on good and reasonable
judgement.

I really appreciate the following comment:
You are extraordinarily stubborn. It is one of my personal
characteristics.

I really throw away all trashes into my backyard garbage bin in the
topics.

I will think a few days to give you a satisfactory answer.

Weng