V
Vagant
Hurrah! It works! I have used 50MHz clock as input and my 1Hz output
signal was connected to a LED. So it flashes every second now! Thanks
to all for encouragement, criticism, real help and suggestions!
P.S. Final version of the VHDL code used is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sig_gen is
Port (clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
clk_out : out STD_LOGIC);
end entity sig_gen;
architecture Behavioral of sig_gen is
signal clk_sig : std_logic;
begin
process(reset_n,clk)
variable cnt : integer;
begin
if (reset_n='0') then
clk_sig<='0';
cnt:=0;
elsif rising_edge(clk) then
if (cnt=24999999) then
clk_sig<=NOT(clk_sig);
cnt:=0;
else
cnt:=cnt+1;
end if;
end if;
end process;
clk_out <= clk_sig;
end Behavioral;
signal was connected to a LED. So it flashes every second now! Thanks
to all for encouragement, criticism, real help and suggestions!
P.S. Final version of the VHDL code used is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sig_gen is
Port (clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
clk_out : out STD_LOGIC);
end entity sig_gen;
architecture Behavioral of sig_gen is
signal clk_sig : std_logic;
begin
process(reset_n,clk)
variable cnt : integer;
begin
if (reset_n='0') then
clk_sig<='0';
cnt:=0;
elsif rising_edge(clk) then
if (cnt=24999999) then
clk_sig<=NOT(clk_sig);
cnt:=0;
else
cnt:=cnt+1;
end if;
end if;
end process;
clk_out <= clk_sig;
end Behavioral;